公开(公告)号：US20080169843A1

公开(公告)日：2008-07-17

申请号：US11872763

申请日：2007-10-16

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G01R19/00

CPC分类号： G11C17/18 ,  G01R31/07 ,  G11C17/165 ,  G11C29/02 ,  G11C29/026 ,  G11C29/027

摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击，并且提供了一个设在该电路中的设计结构。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US20080157851A1

公开(公告)日：2008-07-03

申请号：US11872873

申请日：2007-10-16

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： H01H37/76 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

摘要翻译： 一种用于电可编程熔丝检测电路的设计结构，其具有电可编程熔丝和参考电阻。 第一电流源通过第一开关耦合到电可编程保险丝。 第二电流源通过第二开关耦合到参考电阻。 预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。 当预充电信号不起作用时，第一电流源和第二电流源被切断，并且同时第一开关和第二开关断开。 当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

公开(公告)号：US20080117695A1

公开(公告)日：2008-05-22

申请号：US11560428

申请日：2006-11-16

申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Derick Gardner Behrends ,  George Francis Paulik

发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Derick Gardner Behrends ,  George Francis Paulik

IPC分类号： G11C7/00 ,  G11C8/10

CPC分类号： G11C8/10

摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.

摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。

公开(公告)号：US20080106323A1

公开(公告)日：2008-05-08

申请号：US11550960

申请日：2006-10-19

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： H01H37/76

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

摘要翻译： 一种具有电可编程熔丝和参考电阻的电可编程熔丝检测电路。 第一电流源通过第一开关耦合到电可编程保险丝。 第二电流源通过第二开关耦合到参考电阻。 预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。 当预充电信号不起作用时，第一电流源和第二电流源被切断，同时第一开关和第二开关断开。 当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

公开(公告)号：US07206236B1

公开(公告)日：2007-04-17

申请号：US11330693

申请日：2006-01-12

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Elizabeth Lair Gerhard ,  George Francis Paulik

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Elizabeth Lair Gerhard ,  George Francis Paulik

IPC分类号： G11C29/00

CPC分类号： G11C29/848

摘要： Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.

摘要翻译： 使用冗余位线修复具有多个独立故障的诸如SRAM，DRAM，CAM和可编程ROM的阵列。 第一实施例在阵列的一侧提供冗余位线。 在写入期间，数据将朝着阵列一侧的冗余位线移动，绕过故障位线。 第二实施例在阵列的每一侧提供备用位线。 在写入期间，第一故障位线由阵列的第一侧上的第一备用位线替代，并且第二故障位线被阵列的第二侧上的第二备用位线替代。

公开(公告)号：US06643804B1

公开(公告)日：2003-11-04

申请号：US09552410

申请日：2000-04-19

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

IPC分类号： G11C2900

CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C2029/1204

摘要： An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stability may be made. Stress is applied to a memory cell through the use of a bitline precharge stress operation, which utilizes the bitline pairs coupled to a memory cell to attempt to flood the memory cell with charge and thereby attempt to cause the memory cell to unexpectedly switch state. The bitline precharge stress operation is performed immediately after the memory cell has been switched to one state after being maintained in an opposite state for a length of time that is sufficient to introduce switching history effects to the memory cell. While a bitline precharge operation may be implemented separate from any write operation, the bitline precharge stress operation may also be incorporated into a write operation through delaying the deassertion of the wordline that occurs in a conventional write operation until after initiation of the bitline precharge operation that conventionally occurs near the end of such a write operation.

摘要翻译： 一种测试绝缘体上硅（SOI）静态随机存取存储器（SRAM）的装置，程序产品和方法在测试期间向存储器单元引入开关历史效应以对存储单元施加压力，从而稳定性的可靠确定可以是 制作。 通过使用位线预充电应力操作将应力施加到存储器单元，其利用耦合到存储器单元的位线对尝试以充电方式溢出存储器单元，从而尝试使存储器单元意外地切换状态。 在将存储单元切换到一个状态之后，立即执行位线预充电应力操作，并将其保持在相反的状态，持续足以将切换历史效应引入存储单元的时间长度。 尽管位线预充电操作可以与任何写操作分开实施，但是位线预充电应力操作也可以通过延迟在常规写操作中发生的字线的取消取消而被并入到写操作中，直到在开始位线预充电操作之后， 通常在这种写入操作的结束附近发生。

公开(公告)号：US06181614B2

公开(公告)日：2001-01-30

申请号：US09439974

申请日：1999-11-12

申请人： Anthony Gus Aipperspach ,  Charles Porter Geer

发明人： Anthony Gus Aipperspach ,  Charles Porter Geer

IPC分类号： G11C700

CPC分类号： G11C29/72 ,  G11C29/4401 ,  G11C2029/0407

摘要： A circuit arrangement and method of dynamically repairing a redundant memory array utilize dynamically-determined repair information, generated from a memory test performed on the redundant memory array, along with persistently-stored repair information to repair the redundant memory array. In one implementation, for example, the persistent repair information is generated during manufacture to repair manufacturing defects in the array, with the dynamic repair information generated during a power-on reset of the array to address any additional faults arising after initial manufacture and repair of the array. Furthermore, repair of dynamically-determined errors may utilize otherwise unused redundant memory cells in a redundant memory array, thus minimizing the additional circuitry required to implement dynamic repair functionality with an array.

摘要翻译： 动态修复冗余存储器阵列的电路装置和方法利用从对冗余存储器阵列执行的存储器测试产生的动态确定的修复信息，以及持续存储的修复信息来修复冗余存储器阵列。 在一个实现中，例如，在制造期间生成持久修复信息以修复阵列中的制造缺陷，其中在阵列的上电复位期间产生的动态修复信息以解决在初始制造和修复之后出现的任何附加故障 阵列。 此外，动态确定的错误的修复可以利用冗余存储器阵列中的未使用的冗余存储器单元，从而最小化利用阵列来实现动态修复功能所需的附加电路。

公开(公告)号：US6060909A

公开(公告)日：2000-05-09

申请号：US63534

申请日：1998-04-21

申请人： Anthony Gus Aipperspach ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Gregory John Uhlmann

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An improved compound domino logic circuit is provided. The compound domino logic circuit includes a dynamic logic section and an output driver section. The dynamic logic section includes a clock source providing a clock signal defining an evaluate mode during each high clock cycle and a precharge mode during each low clock cycle. The dynamic logic section includes at least two input nodes for receiving at least two input signals during each evaluate mode. The dynamic logic section includes an output driver input node providing an dynamic output signal during each evaluate mode. The output driver section receives the dynamic output signal and provides an output signal. The output driver section includes a latch for maintaining the output signal during a next precharge mode of the dynamic logic section. A clocked field effect transistor coupled to the output driver input node isolates the dynamic logic section from the output driver section. The output driver section includes a first inverter and a second inverter connected in series to provide the output signal at the output of the second inverter. The output driver section latch is provided by a tristate feedback device connected across the first inverter. The tristate feedback device is enabled only during the precharge mode of the dynamic logic section.

摘要翻译： 提供了一种改进的复合多米诺逻辑电路。 复合多米诺逻辑电路包括动态逻辑部分和输出驱动器部分。 动态逻辑部分包括时钟源，其提供在每个低时钟周期期间在每个高时钟周期期间定义评估模式的时钟信号和预充电模式。 动态逻辑部分包括用于在每个评估模式期间接收至少两个输入信号的至少两个输入节点。 动态逻辑部分包括在每个评估模式期间提供动态输出信号的输出驱动器输入节点。 输出驱动器部分接收动态输出信号并提供输出信号。 输出驱动器部分包括用于在动态逻辑部分的下一个预充电模式期间保持输出信号的锁存器。 耦合到输出驱动器输入节点的定时场效应晶体管将动态逻辑部分与输出驱动器部分隔离。 输出驱动器部分包括串联连接的第一反相器和第二反相器，以在第二反相器的输出处提供输出信号。 输出驱动器部分锁存器由连接在第一反相器上的三态反馈装置提供。 三态反馈装置仅在动态逻辑部分的预充电模式期间使能。

公开(公告)号：US5991224A

公开(公告)日：1999-11-23

申请号：US84127

申请日：1998-05-22

申请人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger ,  Peder James Paulson

发明人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger ,  Peder James Paulson

IPC分类号： G11C8/14 ,  G11C8/16 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C8/14

摘要： A global wire management apparatus and method for a multiple port random access memory (RAM) is disclosed. The RAM includes an array of stacked dual memory cell structures each including a common row/column decoder disposed between an upper memory cell and lower memory cell. The upper memory cell is situated adjacent upper transfer gate circuitry, and the lower memory cell is situated adjacent lower transfer gate circuitry. The decoder circuit is oriented vertically in the middle of the dual memory cell structure so that the true and complement decoder outputs may be fed upwards and downwards to the upper and lower transfer gate circuits. Wiring of the upper and lower transfer gate circuits may be effected completely at the local interconnect layer. Each of the write ports of the common decoder includes a NAND gate, an inverter, and a transfer gate for each of the upper and lower memory cells for controlling the transfer of data to the upper and lower memory cells. The disclosed global wiring management methodology provides an approach for reducing the number of global interconnect wires in a multiple port random access memory cell by sharing various wiring channels between memory cells. Such an approach allows a number of the memory cell global signal interconnects to be moved from the global wiring plane to the local wiring plane.

摘要翻译： 公开了一种用于多端口随机存取存储器（RAM）的全局线管理装置和方法。 RAM包括堆叠的双存储器单元结构的阵列，每个阵列包括布置在上部存储器单元和下部存储器单元之间的公共行/列解码器。 上存储器单元位于上传输门电路附近，并且下存储器单元位于下传输门电路附近。 解码器电路在双存储单元结构的中间垂直取向，使得真和补码解码器输出可以向上和向下馈送到上传输门电路和下传输门电路。 上部和下部传输门电路的接线可以在局部互连层完全实现。 公共解码器的每个写入端口包括用于控制向上部和下部存储器单元传输数据的上部和下部存储器单元中的每一个的“与非”门，反相器和传输门。 所公开的全局布线管理方法提供了一种通过在存储器单元之间共享各种布线通道来减少多端口随机存取存储单元中的全局互连线数量的方法。 这种方法允许多个存储单元全局信号互连从全局布线平面移动到局部布线平面。

公开(公告)号：US07689950B2

公开(公告)日：2010-03-30

申请号：US11872763

申请日：2007-10-16

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G06F17/50

CPC分类号： G11C17/18 ,  G01R31/07 ,  G11C17/165 ,  G11C29/02 ,  G11C29/026 ,  G11C29/027

摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击，并且提供了一个设在该电路中的设计结构。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。