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    Level-shifting transparent window sense amplifier
    32.
    发明授权
    Level-shifting transparent window sense amplifier 有权

    公开(公告)号：US11164611B1

    公开(公告)日：2021-11-02

    申请号：US16906647

    申请日：2020-06-19

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Ajay Bhatia

    IPC: G11C7/00 ,  G11C7/08 ,  H03K19/0185 ,  G11C7/22 ,  G11C7/10 ,  H03K3/037

    Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.

    Low voltage clock swing tolerant sequential circuits for dynamic power savings
    33.
    发明授权
    Low voltage clock swing tolerant sequential circuits for dynamic power savings 有权

    公开(公告)号：US11018653B1

    公开(公告)日：2021-05-25

    申请号：US16866307

    申请日：2020-05-04

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

    IPC: H03K3/012 ,  H03K3/037

    Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

    Low power clock gating circuit
    36.
    发明授权
    Low power clock gating circuit 有权

    公开(公告)号：US10461747B2

    公开(公告)日：2019-10-29

    申请号：US15710406

    申请日：2017-09-20

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Michael R Seningen ,  Ajay Bhatia

    IPC: H03K19/00 ,  H03K5/134

    Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

    Adaptive diode sizing techniques for reducing memory power leakage
    37.
    发明授权
    Adaptive diode sizing techniques for reducing memory power leakage 有权

    公开(公告)号：US09922699B1

    公开(公告)日：2018-03-20

    申请号：US15365361

    申请日：2016-11-30

    Applicant: Apple Inc.

    Inventor： Yildiz Sinangil ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Ajay Bhatia

    IPC: G11C11/00 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

    CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

    Abstract: Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.

    Multistage low leakage address decoder using multiple power modes
    38.
    发明授权
    Multistage low leakage address decoder using multiple power modes 有权
    多级低泄漏地址解码器采用多种功率模式

    公开(公告)号：US09411391B2

    公开(公告)日：2016-08-09

    申请号：US14269841

    申请日：2014-05-05

    Applicant: Apple Inc.

    Inventor： Ajay Bhatia ,  Michael Dreesen

    IPC: G06F1/32 ,  G11C5/14 ,  G06F12/06 ,  G06F12/02 ,  G11C7/10 ,  G11C11/419

    CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

    Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.

    Abstract translation: 一种用于管理存储器中的电力的系统和方法，其中所述系统可以包括处理器和耦合到所述处理器的存储器单元。 存储单元可以将地址解码器初始化为第一功率模式。 响应于接收到与存储器单元内的位置相对应的命令和地址，存储器单元可以使用地址解码器的第一级来解码地址的至少一部分。 存储器单元还可以将地址解码器的第二级的选定部分从第一功率模式切换到第二功率模式，其中地址解码器的第二级的选择部分取决于第一级的第一级的输出信号 地址解码器的阶段。

    MEMORY ARRAY VOLTAGE SOURCE CONTROLLER FOR RETENTION AND WRITE ASSIST
    39.
    发明申请
    MEMORY ARRAY VOLTAGE SOURCE CONTROLLER FOR RETENTION AND WRITE ASSIST 有权
    记忆阵列电压源控制器用于保持和写入

    公开(公告)号：US20140169075A1

    公开(公告)日：2014-06-19

    申请号：US13717870

    申请日：2012-12-18

    Applicant: APPLE INC.

    Inventor： Ajay Bhatia ,  Hang Huang

    IPC: G11C5/14 ,  G11C11/00 ,  G11C7/00

    CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C11/00 ,  G11C11/417

    Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.

    Abstract translation: 用于存储器阵列的电压源控制器包括耦合到电压源的输入端，耦合到存储器阵列的一个或多个存储器单元的输出，其中输出被配置为向存储器单元提供单元源电压。 控制器还包括一个开关电路，其被配置为：接收保持使能信号，写辅助使能信号和标准模式使能信号; 并且基于保持使能信号，写入辅助使能信号和标准模式使能信号，选择性地将一个或多个存储器单元的单元电源电压设置为以下之一：保持电压，写入辅助电压或标准模式 电压，其中保持电压和写入辅助电压小于标准模式电压。

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