公开(公告)号：US20170084247A1

公开(公告)日：2017-03-23

申请号：US14860397

申请日：2015-09-21

Applicant: APPLE INC.

Inventor： Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Patrick B. Bennett ,  Shih Chang Chang ,  Wonjae Choi ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Xinyu Zhu

IPC: G09G5/00

CPC classification number: G09G5/003 ,  G02F2001/13456 ,  G09G3/20 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2330/021

Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.

公开(公告)号：US20170084214A1

公开(公告)日：2017-03-23

申请号：US15162974

申请日：2016-05-24

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Ivan Knez ,  Patrick B. Bennett ,  Shih Chang Chang ,  Byung Duk Yang

IPC: G09G3/20 ,  H01L27/12

CPC classification number: G09G3/20 ,  G02F1/136286 ,  G02F2001/13456 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/08 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0209 ,  G09G2320/0219 ,  H01L27/124

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

公开(公告)号：US09293102B1

公开(公告)日：2016-03-22

申请号：US14504215

申请日：2014-10-01

Applicant: Apple Inc.

Inventor： Hao-Lin Chiu ,  Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。

公开(公告)号：US08823003B2

公开(公告)日：2014-09-02

申请号：US13629537

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/10 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。