公开(公告)号：US20210224949A1

公开(公告)日：2021-07-22

申请号：US16748721

申请日：2020-01-21

Applicant: Arm Limited

Inventor： Alexander Eugene Chalfin ,  Andreas Due Engh-Halstvedt ,  Olof Henrik Uhrenholt

IPC: G06T3/40 ,  G06T1/20 ,  G06T5/00

Abstract: A graphics processor that rasterises input primitives to generate graphics fragments to be processed and renders the graphics fragments to generate a first, higher resolution version of a render output. When processing of a render output is stopped before the render output is finished, the first resolution version of the render output is downsampled to a second, lower resolution and the downsampled data elements at the second resolution are written out together with a set of difference values indicative of the differences between the data elements at the first resolution and the downsampled data elements at the second resolution. Then, when processing of the render output is resumed, these values can be loaded in and used to reconstruct the array of data elements at the first resolution for use when continuing processing of the render output.

公开(公告)号：US20210216464A1

公开(公告)日：2021-07-15

申请号：US16742519

申请日：2020-01-14

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Andreas Due Engh-Halstvedt

IPC: G06F12/0891 ,  G06F9/54 ,  G06F12/0893 ,  G06F12/02 ,  G06F9/30 ,  G06F12/0811

Abstract: In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.

公开(公告)号：US20210158598A1

公开(公告)日：2021-05-27

申请号：US16697984

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Ian Rudolf Bratt ,  Andreas Due Engh-Halstvedt ,  Alexander Eugene Chalfin ,  Andreas Loeve Selvik ,  Olof Henrik Uhrenholt ,  Thomas J. Olson

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions (40) for rendering, each region (40) comprising a respective area of the render output; and for sets of one or more primitives to be rendered, it is determined for which of the plurality of regions of the render output (40) the primitive(s) should be rendered; and for each region of the render output (40) it is determined the primitive(s) should be rendered for, geometry data for the primitive(s) is stored in memory in a respective data structure (42) along with an indication of state data that is to be used for rendering the primitive(s) for the region, such that the geometry data for the primitive(s) to be rendered is stored in a respective, different data structure (42) for each different region of the render output (40) it is determined the primitive(s) should be rendered for.

公开(公告)号：US20200111247A1

公开(公告)日：2020-04-09

申请号：US16153359

申请日：2018-10-05

Applicant: Arm Limited

Inventor： Frode Heggelund ,  Andreas Due Engh-Halstvedt ,  Christian Vik Grovdal

IPC: G06T15/00 ,  G06T15/40 ,  G06T1/20

Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.

公开(公告)号：US10388057B2

公开(公告)日：2019-08-20

申请号：US16029619

申请日：2018-07-08

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Jorn Nystad ,  Andreas Due Engh-Halstvedt

IPC: G09G5/02 ,  G09G5/393 ,  G06T15/04 ,  G06T15/00 ,  G06T3/40 ,  G06T1/20 ,  G06T1/60

Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.

公开(公告)号：US20190138458A1

公开(公告)日：2019-05-09

申请号：US15806237

申请日：2017-11-07

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Langtind ,  Shareef Justin Jalloq

IPC: G06F12/1045 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0891

CPC classification number: G06F12/1045 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/126 ,  G06F2212/50 ,  G06F2212/683

Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

公开(公告)号：US20190019323A1

公开(公告)日：2019-01-17

申请号：US16029619

申请日：2018-07-08

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Jorn Nystad ,  Andreas Due Engh-Halstvedt

IPC: G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T3/4007 ,  G06T15/04 ,  G09G5/02 ,  G09G5/393

Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.

公开(公告)号：US20170024847A1

公开(公告)日：2017-01-26

申请号：US15208459

申请日：2016-07-12

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  David James Bermingham ,  Amir Kleen ,  Jørn Nystad ,  Kenneth Edvard Østby

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: A graphics processing unit 3 includes a rasteriser 25, a thread spawner 40, a programmable execution unit 41, a varying interpolator 42, a texture mapper 43, and a blender 29. The programmable execution unit 41 is able to communicate with the varying interpolator 42, the texture mapper 43 and the blender 29 to request processing operations by those graphic specific accelerators. In addition to this, these graphics-specific accelerators are also able to communicate directly with each other and with the thread spawner 40, independently of the programmable execution unit 41. This allows for certain graphics processing operations to be performed using direct communication between the graphics-specific accelerators of the graphics processing unit, instead of executing instructions in the programmable execution unit to trigger the performance of those operations by the graphics-specific accelerators.

Abstract translation: 图形处理单元3包括光栅化器25，线程器40，可编程执行单元41，变化内插器42，纹理映射器43和混合器29.可编程执行单元41能够与变化内插器42 ，纹理映射器43和混合器29，以请求那些图形特定加速器的处理操作。 除此之外，这些特定于图形的加速器还能够独立于可编程执行单元41彼此直接地与线程线程器40进行通信。这允许使用图形之间的直接通信执行某些图形处理操作 而不是执行可编程执行单元中的指令以触发图形特定加速器对这些操作的执行。

公开(公告)号：US08978038B2

公开(公告)日：2015-03-10

申请号：US13909149

申请日：2013-06-04

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  Jorn Nystad

IPC: G06F9/46 ,  G06F9/48 ,  G06T1/20

CPC classification number: G06F9/46 ,  G06F9/4881 ,  G06F2209/483 ,  G06F2209/484 ,  G06T1/20 ,  Y02D10/24

Abstract: A thread group generator generates from a received workload a plurality of thread groups. Each thread group consists of a plurality of threads, and at least one thread group has an interthread dependency existing between the plurality of threads. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. A thread execution unit then executes each thread within a thread group received from the generator by executing a predetermined program. Execution flow modification circuitry is responsive to the received thread group having at least one dummy thread, to cause the unit to selectively omit at least part of the execution of at least one of the plurality of instructions when executing each dummy thread.

Abstract translation: 线程组生成器从接收的工作负载生成多个线程组。 每个线程组由多个线程组成，并且至少一个线程组在多个线程之间存在间间线依赖关系。 每个线程可以是要求其输出来形成结果数据的活动线程，也可以是解决对其中一个活动线程但不需要输出结果数据的线程间依赖性所需的虚拟线程。 线程执行单元然后通过执行预定程序来执行从发生器接收到的线程组内的每个线程。 执行流修改电路响应于具有至少一个虚拟线程的所接收的线程组，以使得当执行每个虚拟线程时，该单元选择性地省略至少一个执行多个指令中的至少一个指令。

公开(公告)号：US20250111576A1

公开(公告)日：2025-04-03

申请号：US18478666

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Rafal Stepuch ,  Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T15/00 ,  G06T15/04

Abstract: When preparing and storing primitive lists in a tile-based graphics processing system, one or more primitive list pointer arrays store pointers, each pointer indicating a location in storage of one or more of the primitive lists. A further pointer array stores further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays.