公开(公告)号：US11588477B2

公开(公告)日：2023-02-21

申请号：US17128800

申请日：2020-12-21

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US20210111711A1

公开(公告)日：2021-04-15

申请号：US17128800

申请日：2020-12-21

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US20210110867A1

公开(公告)日：2021-04-15

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US20210110853A1

公开(公告)日：2021-04-15

申请号：US16600483

申请日：2019-10-12

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes van Windelhoff ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

公开(公告)号：US10943670B1

公开(公告)日：2021-03-09

申请号：US16555964

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC: G11C7/14 ,  G11C5/06 ,  G11C8/14 ,  G11C29/00 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/16

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US20190198064A1

公开(公告)日：2019-06-27

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/22 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US20190122724A1

公开(公告)日：2019-04-25

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  H01L23/528

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US10074410B2

公开(公告)日：2018-09-11

申请号：US15282532

申请日：2016-09-30

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

公开(公告)号：US20180096715A1

公开(公告)日：2018-04-05

申请号：US15282532

申请日：2016-09-30

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

公开(公告)号：US09711243B1

公开(公告)日：2017-07-18

申请号：US15188876

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Jitendra Dasani ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C29/00 ,  G11C11/412 ,  G11C11/417

CPC classification number: G11C29/76 ,  G11C11/417 ,  G11C29/12 ,  G11C29/842 ,  G11C29/846

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first memory cell array disposed in a first area of the integrated circuit. The first memory cell array includes first memory cells. The integrated circuit may include a second memory cell array disposed in a second area of the integrated circuit that is different than the first area. The second memory cell array includes redundant memory cells that are separate from the first memory cells.