-
公开(公告)号：US20240412918A1
公开(公告)日：2024-12-12
申请号：US18696964
申请日：2023-08-01
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hao ZHANG , Mengyang WEN , Libin LIU , Shiming SHI , Haijun QIU
Abstract: The present disclosure provides a coil structure. The coil structure includes: a dielectric substrate; and a coil portion and a first pattern disposed on the dielectric substrate; wherein the first pattern extends through at least a portion of the dielectric substrate along a thickness direction of the dielectric substrate, and the first pattern is not overlapped with the coil portion.
-
公开(公告)号：US20240371329A1
公开(公告)日：2024-11-07
申请号：US18572742
申请日：2023-05-31
Inventor： Miao LIU , Xueguang HAO , Libin LIU , Teng CHEN , Xinyin WU , Yong QIAO , Xing YAO , Jingquan WANG
IPC: G09G3/3266 , G09G3/20 , G09G3/3233 , G11C19/28 , H10K59/121 , H10K59/126
Abstract: The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area.
-
公开(公告)号：US20240321197A1
公开(公告)日：2024-09-26
申请号：US18027376
申请日：2022-05-12
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang SHANG , Jiangnan LU , Li WANG , Mengyang WEN , Xing YAO , Libin LIU
IPC: G09G3/3233 , G09G3/3266 , G09G3/3275
CPC classification number: G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G2310/08 , G09G2320/0247 , G09G2330/021
Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.
-
公开(公告)号：US20240290271A1
公开(公告)日：2024-08-29
申请号：US18044967
申请日：2022-06-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhenzhen SHAN , Jiangnan LU , Guangliang SHANG , Libin LIU , Jianchao ZHU , Xing YAO
IPC: G09G3/3258
CPC classification number: G09G3/3258 , G09G2300/0426
Abstract: A display substrate includes a driving module arranged on the base substrate, the driving module includes a plurality of driving units, and the driving unit includes a plurality of stages of driving circuits; the driving unit includes a first signal line, and the driving circuit includes an output sub-circuit; the display substrate includes at least two metal layers stacked along a direction away from the base substrate; in at least one driving unit, an orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a first electrode or a second electrode of at least one transistor included in the output sub-circuit on the base substrate, the first electrode and the second electrode are arranged on the same metal layer, and the first electrode and the first signal line are arranged on different metal layers.
-
公开(公告)号：US20240251615A1
公开(公告)日：2024-07-25
申请号：US18406720
申请日：2024-01-08
Applicant: BOE Technology Group Co., Ltd.
IPC: H10K59/131 , H10K59/121
CPC classification number: H10K59/131 , H10K59/1213 , H10K59/1216 , H10K59/1315
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a first reference voltage line, a second reference voltage line and a first reference voltage auxiliary line, the first reference voltage line, the second reference voltage line and the first reference voltage auxiliary line are respectively disposed in one of a second wiring layer, a third wiring layer and a fourth wiring layer, the first reference voltage line is electrically coupled to the first reference voltage auxiliary line through via holes penetrating an insulating layer therebetween, the first reference voltage line and the first reference voltage auxiliary line extend in different directions, the second reference voltage line and the first reference voltage auxiliary line extend in a same direction, the first reference voltage line extends in a row or column direction, and the second reference voltage line extends in the row or column direction.
-
Patent Agency Ranking
公开(公告)号：US20240172503A1
公开(公告)日：2024-05-23
申请号：US18430616
申请日：2024-02-01
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC: H10K59/131 , G09G3/3225 , H10K59/121 , H10K71/00 , H10K59/12 , H10K59/35
CPC classification number: H10K59/131 , G09G3/3225 , H10K59/1213 , H10K59/1216 , H10K71/00 , G09G2300/0426 , G09G2300/0465 , G09G2300/0842 , H10K59/1201 , H10K59/351
Abstract: The present disclosure provides a display panel, a method of manufacturing the same, and a display device. The initialization signal line layer in the display panel includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas; the first auxiliary signal line layer includes a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area, at least part of the first auxiliary signal line pattern extends along the first direction, and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled.
-
公开(公告)号：US20240155905A1
公开(公告)日：2024-05-09
申请号：US18279305
申请日：2021-10-22
Applicant: .BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jianchao ZHU , Shiming SHI , Libin LIU
IPC: H10K59/35 , H10K59/126 , H10K59/131 , H10K59/80 , H10K59/88 , H10K102/00
CPC classification number: H10K59/353 , H10K59/126 , H10K59/131 , H10K59/80518 , H10K59/80524 , H10K59/88 , H10K2102/3031
Abstract: The present invention provides a display panel and a display apparatus, for use in achieving double-sided display. The display panel provided by embodiments of the present invention comprises: a transparent substrate comprising a display region, the display region comprising a plurality of first light emitting regions arranged in an array mode along a first direction and a second direction, and a plurality of second light emitting regions arranged in an array mode along the first direction and the second direction, the first light emitting regions and the second light emitting regions being alternately arranged along a third direction, the first direction intersecting with the second direction, and the third direction intersecting with both the first direction and the second direction.
-
公开(公告)号：US20240013699A1
公开(公告)日：2024-01-11
申请号：US18307853
申请日：2023-04-27
Applicant: BOE Technology Group Co., Ltd.
CPC classification number: G09G3/2074 , G09G3/32 , G09G2300/0408 , G09G2310/0208 , G09G2310/0262
Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate, and a first display region and a second display region that are located on the base substrate, where the first display region includes a plurality of first sub-pixels and a plurality of transparent regions, the second display region includes a plurality of second sub-pixels, and a distribution density of the first sub-pixels is smaller that of the second sub-pixels; and an area occupied by the first sub-pixels is smaller than that occupied by the second sub-pixels.
-
公开(公告)号：US20230380227A1
公开(公告)日：2023-11-23
申请号：US17630172
申请日：2021-03-22
Applicant: BOE Technology Group Co., Ltd.
IPC: H10K59/131 , H10K59/121 , H10K59/12
CPC classification number: H10K59/131 , H10K59/1213 , H10K59/1201
Abstract: A display substrate, a preparation method therefor, and a display apparatus are provided. In a plane parallel to the display substrate, the display substrate includes multiple sub-pixels. At least one sub-pixel includes a pixel driving circuit at least including a drive transistor. An active layer of the drive transistor includes a channel region which includes a drain terminal segment extending in a first direction, an intermediate segment connected to the drain terminal segment, and a source terminal segment connected to the intermediate segment. A first end of the drain terminal away from the intermediate segment has a first width, a second end of the drain terminal segment close to the intermediate segment has a second width. The first width is greater than the second width. The first and second widths are dimensions of the drain terminal segment in a second direction. The first direction intersects with the second direction.
-
公开(公告)号：US20230351970A1
公开(公告)日：2023-11-02
申请号：US17636898
申请日：2021-03-24
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiangnan LU , Guangliang SHANG , Libin LIU , Li WANG , Xinshe YIN , Shiming SHI
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2310/0286 , G11C19/28
Abstract: Provided is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units; a shift register unit includes an input sub-circuit and a denoising output sub-circuit. The denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines. The third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction.
-
-
-
-
-
-
-
-
-
Search Results
170
records
(took 0.036 seconds)
