Abstract:
An array substrate is provided. The array substrate includes a base substrate, and a buffer layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source/drain metal layer and a pixel electrode layer that are subsequently formed on the base substrate, and a common electrode layer formed between the base substrate and the buffer layer. The array substrate has an increased storage capacitance and an improved maintenance ratio of pixel voltage, suppresses the unfavorable phenomenon like flicker of the display device. A method for manufacturing an array substrate and a display device including such an array substrate are also provided.
Abstract:
The invention discloses a capacitive in-cell touch panel and a display device. Since at least two neighboring gate lines on a common array substrate and the gates connected with them serve as a first touch sensing electrode, at least two neighboring data lines on the common array substrate and the sources connected with them serve as a second touch sensing electrode, and there is no need to further add a new film layer on the existing array substrate, this may reduce the number of masking in the production process, decrease the thickness of the touch panel and lower the production cost; moreover, a time divisional driving mode is adopted in the touch-control time period and the display time period, which may avoid the interference between the display signal and the touch-control driving signal, and guarantee the quality of a display picture and the accuracy of the touch-control.
Abstract:
A thin film transistor (TFT) array substrate is disclosed and having a pixel region and a peripheral region surrounding the pixel region, and the pixel region comprises horizontal gate lines, longitudinal data lines defining pixel units with the horizontal gate lines, and storage capacitor electrode (Vcom) lines. The peripheral region comprises at least one peripheral common electrode line which is electrically connected with an integrated-circuit (IC) element. The Vcom lines are connected with the peripheral common electrode line through one or more Vcom line IC terminals.
Abstract:
An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially.
Abstract:
The present invention provides an array substrate and a display panel. The array substrate comprises a plurality of data lines and a plurality of common electrode lines, wherein, the array substrate further comprises at least one discharge unit, each discharge unit corresponds to one of the plurality of data lines and is connected between the corresponding data line and one of the plurality of common electrode lines, and each discharge unit can selectively conduct the data line to the common electrode line connected thereto. The display panel comprises the array substrate. In the present invention, the discharge unit can selectively conduct the data line connected thereto to the common electrode line connected thereto, to enable fast discharge of the storage capacitance and reduce occurrence of afterimage phenomenon.
Abstract:
An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a metal shield layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer sequentially formed on the base substrate. At least one first via hole penetrating to the metal shield layer is formed in the interlayer dielectric layer and the gate insulation layer. The source-drain metal layer is formed in the at least one first via hole and on the interlayer dielectric layer having the at least one first via hole.
Abstract:
The present invention discloses an in-cell touch panel and a display device to improve the opening rate of the in-cell touch panel. The in-cell touch panel provided by the embodiment of the present invention comprises a first substrate and a second substrate opposite to each other, a black matrix layer and a color resin layer located at the side of the first substrate close to the second substrate, and a pixel array located at the side of the second substrate close to the first substrate, and further comprises a plurality of first electrodes located on the first substrate or the second substrate and extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first direction; the first electrodes and the second electrodes are disposed at the same layer and insulated from each other; the first electrodes comprise a plurality of electrode units independent of each other, the electrode units and the second electrodes are arranged with an interval therebetween, and two electrode units which belong to the same first electrode and are located at two sides of the second electrodes are electrically connected through a bridge line.
Abstract:
An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially.
Abstract:
The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit and a display apparatus, the shift register unit includes an inputting module, a first outputting module and a second outputting module. As compared with the prior art, the structure of the shift register unit can be simplified effectively, and the number of use of the transistors can be further reduced. Embodiments of the present disclosure are used to implement scanning and driving.
Abstract:
An in-cell touch panel and a display device are configured to address mutual interference between touch signals and image display signals and increase opening ratio of the in-cell touch panel at the same time. The in-cell touch panel includes a color filter substrate and an array substrate disposed opposite to form a cell, a plurality of sub-pixel units arranged in matrix are disposed on said array substrate, and further includes: a plurality of touch sensing electrodes distributed in a column direction of said sub-pixel units on said color filter substrate, and a plurality of touch driving electrodes distributed in a row direction of said sub-pixel units on said array substrate, every two adjacent rows of sub-pixel units constituting a sub-pixel unit group and gate lines for providing gate signals to these two rows of sub-pixel units being disposed between these two rows of sub-pixel units; wherein said touch driving electrodes are located in non-display areas between said sub-pixel unit groups.