公开(公告)号：US08171435B2

公开(公告)日：2012-05-01

申请号：US12720728

申请日：2010-03-10

申请人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

摘要翻译： 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在该电路中，ESD器件被连接到第一金属级（例如，M1）。 电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

公开(公告)号：US08138579B2

公开(公告)日：2012-03-20

申请号：US11867995

申请日：2007-10-05

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L23/58

CPC分类号： H01L29/165 ,  H01L21/84 ,  H01L27/0652 ,  H01L27/1203

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。 本发明还涉及电路所在的设计结构。

公开(公告)号：US07718481B2

公开(公告)日：2010-05-18

申请号：US11279934

申请日：2006-04-17

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L21/8238

CPC分类号： H01L29/7322 ,  H01L27/0921 ,  H01L29/0821 ,  H01L29/66272

摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

摘要翻译： 一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。 该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。 至少一个通孔电连接深子集电极和近子集电极。 该方法包括形成合并三阱双外延/双子集电极。

公开(公告)号：US20090001417A1

公开(公告)日：2009-01-01

申请号：US11867995

申请日：2007-10-05

申请人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/24

CPC分类号： H01L29/165 ,  H01L21/84 ,  H01L27/0652 ,  H01L27/1203

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。 本发明还涉及电路所在的设计结构。

公开(公告)号：US08035190B2

公开(公告)日：2011-10-11

申请号：US12725792

申请日：2010-03-17

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US07989306B2

公开(公告)日：2011-08-02

申请号：US11770908

申请日：2007-06-29

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L21/76 ,  H01L21/322 ,  H01L21/20 ,  H01L21/36 ,  H01L23/58 ,  H01L21/02 ,  H01L29/30

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US20090039385A1

公开(公告)日：2009-02-12

申请号：US12237148

申请日：2008-09-24

申请人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/737 ,  H01L29/00

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US20090001414A1

公开(公告)日：2009-01-01

申请号：US11770908

申请日：2007-06-29

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US20090101887A1

公开(公告)日：2009-04-23

申请号：US11876787

申请日：2007-10-23

申请人： Erik M. Dahlstrom ,  Alvin J. Joseph ,  Robert M. Rassel ,  David C. Sheridan

发明人： Erik M. Dahlstrom ,  Alvin J. Joseph ,  Robert M. Rassel ,  David C. Sheridan

IPC分类号： H01L29/12 ,  H01L21/329

CPC分类号： H01L29/93 ,  H01L29/155 ,  H01L29/165

摘要： Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

摘要翻译： 优化的方法和异质结构屏障变容二极管（HBV）二极管，用于在亚毫米波频率及以上提供输出的频率乘法器。 HBV二极管包括含硅衬底，位于含硅衬底上的电极以及二极管的一个或多个电极的Si和SiGe的交替层的一个或多个异质结量子阱。 每个SiGe量子阱优选地在相邻SiGe梯度之间具有相邻SiGe梯度之间的浮动SiGe层，随后是相邻的Si层，使得提供单一的均匀结构，其特征在于没有明显的分离。 多个Si / SiGe异质结量子阱可以是对称的或不对称的。

公开(公告)号：US07491632B2

公开(公告)日：2009-02-17

申请号：US11164108

申请日：2005-11-10

申请人： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

发明人： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

IPC分类号： H01L21/425

CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。