利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

158 条记录 (耗时 0.026 秒)

    INTEGRATED CIRCUIT STUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM
    1.
    发明申请
    INTEGRATED CIRCUIT STUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM 失效
    一体化电路结合电感器，相关设计方法和相关设计系统

    公开(公告)号：US20080237789A1

    公开(公告)日：2008-10-02

    申请号：US11692948

    申请日：2007-03-29

    申请人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： H01L29/00 ,  G06F17/50

    CPC分类号： G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

    摘要翻译： 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在电路中，ESD器件被连接到第一金属电平（例如，M 1）。 电感器形成在第一金属级上方的第二金属级（例如，M 5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M 3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

    INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM
    2.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM 失效
    集成电路结构，电感设计，相关设计方法和相关设计系统

    公开(公告)号：US20100175035A1

    公开(公告)日：2010-07-08

    申请号：US12720728

    申请日：2010-03-10

    申请人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

    摘要翻译： 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在该电路中，ESD器件被连接到第一金属级（例如，M1）。 电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 电感器被配置为对于给定的应用频率，使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

    Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit
    3.
    发明授权
    Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit 失效
    集成电路结构，包括电感器，导电片和保护电路

    公开(公告)号：US07750408B2

    公开(公告)日：2010-07-06

    申请号：US11692948

    申请日：2007-03-29

    申请人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： H01L23/62

    CPC分类号： G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

    摘要翻译： 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在该电路中，ESD器件被连接到第一金属级（例如，M1）。 电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

    Integrated circuit structure incorporating an inductor, an associated design method and an associated design system
    4.
    发明授权
    Integrated circuit structure incorporating an inductor, an associated design method and an associated design system 失效
    结合电感的集成电路结构，相关设计方法和相关设计系统

    公开(公告)号：US08171435B2

    公开(公告)日：2012-05-01

    申请号：US12720728

    申请日：2010-03-10

    申请人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Zhong-Xiang He ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： G06F17/50 ,  G06F11/22

    CPC分类号： G06F17/5063 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

    摘要翻译： 公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。 在该电路中，ESD器件被连接到第一金属级（例如，M1）。 电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。 对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。 通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。 屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

    Intralevel conductive light shield
    6.
    发明授权
    Intralevel conductive light shield 有权
    Intralevel导电灯罩

    公开(公告)号：US08709855B2

    公开(公告)日：2014-04-29

    申请号：US12133379

    申请日：2008-06-05

    申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    IPC分类号： H01L21/00

    CPC分类号： H01L23/552 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

    摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。

    INTERLEVEL CONDUCTIVE LIGHT SHIELD
    9.
    发明申请
    INTERLEVEL CONDUCTIVE LIGHT SHIELD 有权
    交互式导光灯

    公开(公告)号：US20090303366A1

    公开(公告)日：2009-12-10

    申请号：US12133380

    申请日：2008-06-05

    申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    IPC分类号： H04N5/335

    CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643

    摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

    摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。