公开(公告)号：US20080113476A1

公开(公告)日：2008-05-15

申请号：US12014850

申请日：2008-01-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20070252241A1

公开(公告)日：2007-11-01

申请号：US11767635

申请日：2007-06-25

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/94 ,  H01L21/336 ,  H01L29/76 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

公开(公告)号：US20070249130A1

公开(公告)日：2007-10-25

申请号：US11379581

申请日：2006-04-21

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26586 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851

摘要： Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.

摘要翻译： 公开了一种用于在非平面FET（例如，finFET或触发FET）的多晶硅栅极中诱导应变的技术，以便在FET沟道区上施加类似的应变，同时保护FET的源极/漏极区域 半导体鳍片 具体地，在翅片的源极/漏极区域之上形成保护盖层，以便在随后的悬空离子注入工艺期间保护这些区域。 在该植入过程期间，翅片被进一步保护，因为离子束在平行于翅片并从垂直轴倾斜的平面中朝向栅极。 因此，翅片的非晶化和鳍的损害是有限的。 在注入工艺和形成应变层之后，进行再结晶退火，使得应变层的应变“存储在多晶硅栅极中”。

公开(公告)号：US20070188195A1

公开(公告)日：2007-08-16

申请号：US11276169

申请日：2006-02-16

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

摘要翻译： 提供了一种用于提供用于集成电路芯片的多电压岛/核心架构的驱动器的系统和方法。 互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值 电源（Vdd）在芯片上。 基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。

公开(公告)号：US20070108537A1

公开(公告)日：2007-05-17

申请号：US11164216

申请日：2005-11-15

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

IPC分类号： H01L21/8244

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

公开(公告)号：US20070108528A1

公开(公告)日：2007-05-17

申请号：US11164218

申请日：2005-11-15

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/785 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise non-planar partially depleted three-gated FETs having a greater channel width and a greater gate length and, thus, a greater drive current relative to the pass-gate and pull-up FETs. Additionally, for optimal electron mobility and hole mobility, respectively, the channels of the n-FETs and p-FETs can comprise semiconductors with different crystalline orientations.

摘要翻译： 公开了具有两个通过栅极n-FET，两个上拉p-FET和两个下拉n-FET的SOI，体或HOT晶片上的SRAM单元以及制造SRAM单元的相关方法。 栅极FET和下拉FET是非平面完全耗尽的finFET或触发FET。 下拉式FET包括具有较大沟道宽度和较大栅极长度以及因此相对于栅极和上拉FET的较大驱动电流的非平面部分耗尽的三门式FET。 此外，为了分别实现最佳的电子迁移率和空穴迁移率，n-FET和p-FET的沟道可以包括具有不同结晶取向的半导体。

公开(公告)号：US20070085134A1

公开(公告)日：2007-04-19

申请号：US10596029

申请日：2003-12-08

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/792 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.

摘要翻译： 集成电路半导体存储器件（100）具有第一介电层（116），其特征在于，在存储晶体管的栅极下方的衬底（112）的部分（130）中不存在BOX层，以增加栅极到衬底 电容，从而降低软错误率。 具有不同于第一电介质层的性质的第二电介质层（132）至少部分地覆盖衬底的该部分（130）。 器件可以是FinFET器件，其包括在栅极和鳍之间的鳍（122）和栅极电介质层（124,126），其中第二介电层具有比栅极电介质层更少的泄漏。

公开(公告)号：US20060267111A1

公开(公告)日：2006-11-30

申请号：US11436480

申请日：2006-05-18

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。

公开(公告)号：US20060231929A1

公开(公告)日：2006-10-19

申请号：US11426698

申请日：2006-06-27

申请人： Brent Anderson ,  Edward Nowak ,  BethAnn Rainev

发明人： Brent Anderson ,  Edward Nowak ,  BethAnn Rainev

IPC分类号： H01L29/06

CPC分类号： H01L21/02595 ,  H01L21/02667 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

摘要翻译： 在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。 然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。 然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。 因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

公开(公告)号：US20060160292A1

公开(公告)日：2006-07-20

申请号：US11378786

申请日：2006-03-17

申请人： Brent Anderson ,  Louis Lanzerotti ,  Edward Nowak

发明人： Brent Anderson ,  Louis Lanzerotti ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 该场效应晶体管包括：形成在栅极电介质层的顶表面上的栅电极，单晶硅沟道区的顶表面上的栅介质层，顶表面上的单晶硅沟道区 包含Ge的层，在单晶硅衬底的顶表面上的Ge包括层，在单晶硅衬底的顶表面上的第一介电层和第二电介质层之间的Ge包括层。