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    Systems and methods for congestion and routability aware detailed placement
    31.
    发明授权
    Systems and methods for congestion and routability aware detailed placement 有权

    公开(公告)号：US10031994B1

    公开(公告)日：2018-07-24

    申请号：US15219008

    申请日：2016-07-25

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Wen Hao Liu ,  Jhih-Rong Gao ,  Mehmet Yildiz ,  Charles Alpert ,  Zhuo Li

    IPC: G06F17/50

    Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

    Post-CTS clock tree restructuring
    35.
    发明授权
    Post-CTS clock tree restructuring 有权

    公开(公告)号：US11620428B1

    公开(公告)日：2023-04-04

    申请号：US17315019

    申请日：2021-05-07

    Applicant: Cadence Design Systems, Inc.

    Inventor： Andrew Mark Chapman ,  Zhuo Li

    IPC: G06F30/396 ,  G06F30/367 ,  G06F30/337 ,  G06F30/3312 ,  G06F117/04 ,  G06F119/12 ,  G06F117/10

    Abstract: Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

    Pruning of buffering candidates for improved efficiency of evaluation
    36.
    发明授权
    Pruning of buffering candidates for improved efficiency of evaluation 有权

    公开(公告)号：US11520959B1

    公开(公告)日：2022-12-06

    申请号：US17219742

    申请日：2021-03-31

    Applicant: Cadence Design Systems, Inc.

    Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Jhih-Rong Gao ,  Sheng-En David Lin

    IPC: G06F30/323 ,  G06F9/54

    Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

    PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS
    37.
    发明申请
    PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS 有权

    公开(公告)号：US20220318480A1

    公开(公告)日：2022-10-06

    申请号：US17219748

    申请日：2021-03-31

    Applicant: Cadence Design Systems, Inc.

    Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

    IPC: G06F30/398 ,  G06F30/392

    Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

    Post-CTS clock tree restructuring with ripple move
    39.
    发明授权
    Post-CTS clock tree restructuring with ripple move 有权

    公开(公告)号：US11354479B1

    公开(公告)日：2022-06-07

    申请号：US17315032

    申请日：2021-05-07

    Applicant: Cadence Design Systems, Inc.

    Inventor： Andrew Mark Chapman ,  Zhuo Li

    IPC: G06F30/396 ,  G06F30/398 ,  G06F30/3312 ,  G06F30/337 ,  G06F30/373

    Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

    Machine-learning based prediction method for iterative clustering during clock tree synthesis
    40.
    发明授权
    Machine-learning based prediction method for iterative clustering during clock tree synthesis 有权

    公开(公告)号：US11244099B1

    公开(公告)日：2022-02-08

    申请号：US17139675

    申请日：2020-12-31

    Applicant: Cadence Design Systems, Inc.

    Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  Zhuo Li ,  Yi-Xiao Ding

    IPC: G06F30/396 ,  G06N20/00 ,  G06N5/04 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/392

    Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

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