Nonvolatile memory having overerase protection
    31.
    发明授权
    Nonvolatile memory having overerase protection 失效
    非易失性存储器具有过度保护

    公开(公告)号:US5422846A

    公开(公告)日:1995-06-06

    申请号:US222066

    申请日:1994-04-04

    IPC分类号: G11C16/16 G11C11/40

    CPC分类号: G11C16/16

    摘要: A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.

    摘要翻译: 非易失性存储器(20)包括以行和列组织的浮栅晶体管阵列(22)。 相邻行的字线被耦合在一起以形成共享字线。 在一个实施例中,耦合晶体管(56-61)用于响应于所选择的共享字线将行的浮置栅晶体管(36,39-55)的源耦合到预定电位。 阵列(22)的未选择的浮栅晶体管的源极被隔离。 在另一个实施例中,响应于所选择的共享字线,反相器(113,114和115)将源耦合到零伏特。 响应于共享字线的逻辑状态来控制浮栅晶体管(36,39-55)的电导率,以确保未选择的单元不会不利地影响非易失性存储器的操作。

    Apparatus and method for erasing a flash EEPROM
    32.
    发明授权
    Apparatus and method for erasing a flash EEPROM 失效
    擦除闪存EEPROM的装置和方法

    公开(公告)号:US5357476A

    公开(公告)日:1994-10-18

    申请号:US69327

    申请日:1993-06-01

    IPC分类号: G11C16/16 G11C16/34 G11C11/34

    摘要: A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.

    摘要翻译: 闪存EEPROM阵列(22)被擦除,并且擦除的快闪EEPROM单元(36,39-46)的阈值电压分布通过使用两步擦除过程而被收敛到预定电压范围内。 在第一步中,使用传统的大容量擦除程序,电子体积擦除快闪EEPROM阵列(22)。 电子从浮动栅极(38)隧穿到源极,导致电池(36,39-46)具有相对低的阈值电压。 在第二步骤中,通过使每个单元(36,39-46)的源极和漏极接地而将阵列(22)的阈值电压分布收敛到预定电压范围内,同时向控制器施加高正电压 (36,39-46)的门(27)。 一些电子被隧穿回到浮动栅极(38),从而将阈值电压分布会聚到预定范围内。

    Methods and structures for charge storage isolation in split-gate memory arrays
    33.
    发明授权
    Methods and structures for charge storage isolation in split-gate memory arrays 有权
    分闸存储器阵列中电荷存储隔离的方法和结构

    公开(公告)号:US09136360B1

    公开(公告)日:2015-09-15

    申请号:US14297657

    申请日:2014-06-06

    IPC分类号: H01L29/792 H01L29/66

    摘要: Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.

    摘要翻译: 形成存储器结构包括在衬底上形成电荷存储层; 形成第一控制栅层; 图案化第一控制栅极层以在第一控制栅极层和电荷存储层中形成开口,其中开口延伸到基板中; 用绝缘材料填充开口; 在所述图案化的第一控制栅极层和绝缘材料上形成第二控制栅极层; 图案化第二控制栅极层以形成第一控制栅电极和第二控制栅电极,其中第一控制栅电极包括第一和第二控制栅层中的每一个的第一部分,而第二控制栅电极包括第二部分 并且所述绝缘材料位于所述控制栅电极之间; 以及在控制栅电极附近形成选择栅电极。

    Split gate memory device with gap spacer
    34.
    发明授权
    Split gate memory device with gap spacer 有权
    具有间隔垫片的分离栅存储器件

    公开(公告)号:US08835295B2

    公开(公告)日:2014-09-16

    申请号:US13961574

    申请日:2013-08-07

    IPC分类号: H01L29/423

    摘要: A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.

    摘要翻译: 用于形成分离栅极器件的方法包括形成第一导电栅极层的第一侧壁,其中所述半导体层包括横向邻近所述第一侧壁的隧道区域,沿着所述第一侧壁形成电介质层,以提供增加的间隙厚度 间隔物,在所述第一导电层的顶表面的一部分上并在所述隧道区上方形成电荷存储层,以及在所述电荷存储层上形成第二导电栅极层。

    Method of making a split gate memory cell
    35.
    发明授权
    Method of making a split gate memory cell 有权
    制造分离栅极存储单元的方法

    公开(公告)号:US08173505B2

    公开(公告)日:2012-05-08

    申请号:US12254331

    申请日:2008-10-20

    IPC分类号: H01L21/336

    摘要: A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.

    摘要翻译: 一种方法包括在半导体衬底上形成栅极材料的第一层; 在第一层上形成硬掩模层; 形成开口 在所述硬掩模层和所述开口内形成电荷存储层; 在所述电荷存储层上形成栅极材料的第二层; 去除所述第二层的一部分和所述电荷存储层的覆盖所述硬掩模层的部分,其中所述第二层的第二部分保留在所述开口内; 在所述硬掩模层上并在所述第二部分上形成图案化掩模层,其中所述图案化掩模层限定第一和第二位单元; 以及使用所述图案化掩模层形成所述第一和第二位单元,其中所述第一和第二位单元中的每一个包含由所述第一层制成的选择栅极和由所述第二层制成的控制栅极。

    SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF MAKING
    36.
    发明申请
    SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF MAKING 失效
    自对准分割栅存储单元及其制作方法

    公开(公告)号:US20080121974A1

    公开(公告)日:2008-05-29

    申请号:US11469163

    申请日:2006-08-31

    IPC分类号: H01L29/788 H01L21/336

    摘要: A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer (56,168). The opening is further filled with select gate material (58,170). The sacrificial structure is removed after filling the opening with the select gate material.

    摘要翻译: 使用半导体衬底(12)形成分离栅极存储单元(10,11)的方法包括在衬底上形成选择栅极结构(48)和牺牲结构(50)。 选择栅极结构和牺牲结构之间有一个开口。 开口衬有存储层(56,168)。 开口进一步填充选择栅极材料(58,170)。 在用选择栅极材料填充开口之后去除牺牲结构。

    Silicided nonvolatile memory and method of making same
    37.
    发明申请
    Silicided nonvolatile memory and method of making same 有权
    硅化非易失性存储器及其制造方法

    公开(公告)号:US20070218633A1

    公开(公告)日:2007-09-20

    申请号:US11376410

    申请日:2006-03-15

    IPC分类号: H01L21/336

    摘要: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

    摘要翻译: 存储器件形成在半导体衬底上。 选择栅电极和控制栅电极彼此相邻地形成。 选择栅极电极或控制栅电极中的一个相对于另一个凹陷。 该凹槽允许用于在选择栅极电极和控制栅极电极上形成硅化物表面的可制造工艺。

    Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate
    38.
    发明申请
    Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate 有权
    在半导体衬底上形成非易失性存储器和外围器件的方法

    公开(公告)号:US20070218631A1

    公开(公告)日:2007-09-20

    申请号:US11376411

    申请日:2006-03-15

    IPC分类号: H01L21/336

    摘要: A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present in the first gate electrode. A peripheral transistor area is formed devoid of nanoclusters.

    摘要翻译: 一种用于形成半导体器件的方法包括在半导体衬底上形成第一栅电极,其中第一栅电极包括硅并在半导体衬底上形成并邻近第一栅电极的第二栅电极,其中第二栅电极包括硅。 纳米簇存在于第一栅电极中。 外围晶体管区域形成为没有纳米团簇。

    Process for forming an electrically programmable read-only memory cell
    39.
    发明授权
    Process for forming an electrically programmable read-only memory cell 失效
    用于形成电可编程只读存储器单元的工艺

    公开(公告)号:US5705415A

    公开(公告)日:1998-01-06

    申请号:US324423

    申请日:1994-10-04

    IPC分类号: H01L21/8247 H01L27/115

    CPC分类号: H01L27/11556 H01L27/115

    摘要: A semiconductor device is formed having a floating gate memory cell (11) that has its channel region (33) oriented vertically with a portion of the channel region (33) that is not capacitively coupled to a floating gate (32). The memory cell (11) is less likely to be over-erased and may be programmed by source-side injection. The cell (11) may not need to be repaired after erasing. Less power may be consumed during programming compared to hot electron injection and Fowler-Nordheim tunneling.

    摘要翻译: 形成具有浮动栅极存储单元(11)的半导体器件,其浮动栅极存储单元(11)的沟道区域(33)垂直定向,而沟道区域(33)的一部分不与浮动栅极电容耦合。 存储单元(11)不太可能被过度擦除,并且可以通过源侧注入来编程。 擦除后,电池(11)可能不需要修理。 与热电子注入和Fowler-Nordheim隧道相比,编程期间可能消耗较少的功率。

    Cross-point eeprom memory array
    40.
    发明授权
    Cross-point eeprom memory array 失效
    交叉点eeprom存储器阵列

    公开(公告)号:US5467308A

    公开(公告)日:1995-11-14

    申请号:US223354

    申请日:1994-04-05

    摘要: A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).

    摘要翻译: 交叉点EEPROM存储器阵列包括具有由沟道区域(36)间隔开的第一和第二位线(32,34)的半导体衬底(10)。 控制栅电极(24)由控制栅极线的一部分形成,该部分覆盖在沟道区(36)的第一部分上并由ONO层(17)分离。 选择栅极(40)由垂直于控制栅线的基板(10)上的选择栅线的一部分形成。 通过使用源侧注入将电子注入到ONO层(17)的氮化硅层(14)中的捕获位点(19)中来编程阵列中的各个单元。 通过电子隧道穿过ONO层(17)的顶部二氧化硅层(16)擦除阵列中的电池,并在控制栅电极(24)中消散。 部分地通过将ONO层(17)的第一二氧化硅层(12)制造成比ONO层(17)的顶部二氧化硅层(16)更大的厚度来获得改进的操作性能。