公开(公告)号：US09418830B2

公开(公告)日：2016-08-16

申请号：US14318063

申请日：2014-06-27

Applicant: Jeffrey D. Hanna ,  Robert F. Steimle ,  Michael D. Turner

Inventor： Jeffrey D. Hanna ,  Robert F. Steimle ,  Michael D. Turner

IPC: H01L21/02 ,  B81C1/00

CPC classification number: H01L21/02002 ,  B81C1/00269 ,  H01L21/187 ,  H01L2221/00

Abstract: A method of bonding a cap wafer to a device wafer includes heating the device wafer and the cap wafer in the chamber, cooling the device wafer and the cap wafer in the chamber, pressurizing the chamber, introducing gas into the chamber while the chamber is pressurized to accelerate a rate of one of a group consisting of the heating and the cooling, and applying pressure to the device wafer and the cap wafer while a bond is formed between the device wafer and the cap wafer.

Abstract translation: 将盖晶片接合到器件晶片的方法包括在腔室中加热器件晶片和盖晶片，冷却腔室中的器件晶片和盖晶片，对腔室加压，同时在腔室被加压的同时将气体引入腔室 以加速由加热和冷却组成的组中的一个的速率，以及在器件晶片和盖晶片之间形成结合时向器件晶片和盖晶片施加压力。

公开(公告)号：US09290380B2

公开(公告)日：2016-03-22

申请号：US13718614

申请日：2012-12-18

Applicant: Robert F. Steimle ,  Ruben B. Montez

Inventor： Robert F. Steimle ,  Ruben B. Montez

IPC: B81B3/00 ,  B81C1/00 ,  G01P15/08

CPC classification number: B81B3/001 ,  B81B3/0005 ,  B81B2201/0221 ,  B81B2201/0235 ,  B81B2203/0181 ,  B81B2203/06 ,  B81C1/0096 ,  B81C2201/115 ,  G01P15/0802 ,  G01P2015/0871 ,  G01P2015/0874

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.

Abstract translation: 提供了一种用于通过减小可以紧密接触的两个表面之间的表面积来减小MEMS器件中的静摩擦的机构。 通过增加一个或两个表面的表面粗糙度来实现接触表面积的减小。 通过在用于形成MEMS器件的牺牲层上形成微掩模层，然后蚀刻牺牲层的表面来提供增加的粗糙度。 微掩模层可以使用纳米团簇形成。 当MEMS器件的下一部分形成在牺牲层上时，该部分将通过蚀刻工艺承受赋予牺牲层的粗糙度特性。 较粗糙的表面减小了可用于MEMS器件中的接触的表面积，并且进而降低了可赋予粘性的面积。

公开(公告)号：US20160031698A1

公开(公告)日：2016-02-04

申请号：US14446910

申请日：2014-07-30

Applicant: Robert F. Steimle ,  Ruben B. Montez

Inventor： Robert F. Steimle ,  Ruben B. Montez

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B2201/0235 ,  B81B2203/0181

Abstract: Certain microelectromechanical systems (MEMS) devices, and methods of creating them, are disclosed. The method may include forming a structural layer over a substrate; forming a mask layer over the structural layer, wherein the mask layer is formed with a material selective to an etching process; forming a plurality of nanoclusters on the mask layer; and etching the structural layer using at least the etching process.

Abstract translation: 公开了某些微机电系统（MEMS）设备及其创建方法。 该方法可以包括在衬底上形成结构层; 在所述结构层上形成掩模层，其中所述掩模层由对蚀刻工艺选择的材料形成; 在掩模层上形成多个纳米团簇; 并使用至少蚀刻工艺蚀刻结构层。

公开(公告)号：US20150375995A1

公开(公告)日：2015-12-31

申请号：US14317101

申请日：2014-06-27

Applicant: Robert F. Steimle ,  Paul M. Winebarger

Inventor： Robert F. Steimle ,  Paul M. Winebarger

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C1/00253

Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.

Abstract translation: 描述了一种用于制造具有形成在多层半导体结构（100）和一个或多个盖装置（200）的不同层中的多个垂直堆叠的惯性换能器元件（101B，110D）的高纵横比MEMS传感器装置的方法和装置 ，300），其结合到多层半导体结构（100）以保护任何暴露的惯性换能器元件免受周围环境条件的影响。

公开(公告)号：US07838363B2

公开(公告)日：2010-11-23

申请号：US11931376

申请日：2007-10-31

Applicant: Robert F. Steimle ,  Gowrishankar L. Chindalore ,  Matthew T. Herrick

Inventor： Robert F. Steimle ,  Gowrishankar L. Chindalore ,  Matthew T. Herrick

IPC: H01L21/00

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833

Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.

Abstract translation: 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。

公开(公告)号：US20080026526A1

公开(公告)日：2008-01-31

申请号：US11459837

申请日：2006-07-25

Applicant: Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

Inventor： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/32134 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract translation: 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 在半导体层上形成第一电介质层。 在第一电介质层上进行等离子体氮化。 在第一部分上形成第一多个纳米团簇，并在第二部分上形成第二多个纳米团簇。 第二组纳米团簇被去除。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。

公开(公告)号：US07192876B2

公开(公告)日：2007-03-20

申请号：US10443375

申请日：2003-05-22

Applicant: Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

Inventor： Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

IPC: H01L21/308

CPC classification number: H01L29/785 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7881 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.

Abstract translation: 制造具有独立栅极结构的晶体管的方法。 栅极结构各自与半导体结构的侧壁相邻。 该方法包括在包括沟道区域的半导体结构上沉积包括栅极材料层的至少一个共形层。 在晶片上形成平面层。 平面层在衬底上方的位置处具有在大致最小一个共形层的顶表面下方的顶表面。 蚀刻至少一个共形层以去除半导体结构上的栅极材料。

公开(公告)号：US07160775B2

公开(公告)日：2007-01-09

申请号：US10912825

申请日：2004-08-06

Applicant: Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

Inventor： Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

IPC: H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0475 ,  G11C16/14 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract translation: 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

公开(公告)号：US20150380235A1

公开(公告)日：2015-12-31

申请号：US14318063

申请日：2014-06-27

Applicant: JEFFREY D. HANNA ,  ROBERT F. STEIMLE ,  MICHAEL D. TURNER

Inventor： JEFFREY D. HANNA ,  ROBERT F. STEIMLE ,  MICHAEL D. TURNER

IPC: H01L21/02

CPC classification number: H01L21/02002 ,  B81C1/00269 ,  H01L21/187 ,  H01L2221/00

Abstract: A method of bonding a cap wafer to a device wafer includes heating the device wafer and the cap wafer in the chamber, cooling the device wafer and the cap wafer in the chamber, pressurizing the chamber, introducing gas into the chamber while the chamber is pressurized to accelerate a rate of one of a group consisting of the heating and the cooling, and applying pressure to the device wafer and the cap wafer while a bond is formed between the device wafer and the cap wafer.

Abstract translation: 将盖晶片接合到器件晶片的方法包括在腔室中加热器件晶片和盖晶片，冷却腔室中的器件晶片和盖晶片，对腔室加压，同时在腔室被加压的同时将气体引入腔室 以加速由加热和冷却组成的组中的一个的速率，以及在器件晶片和盖晶片之间形成结合时向器件晶片和盖晶片施加压力。

公开(公告)号：US08633088B2

公开(公告)日：2014-01-21

申请号：US13460020

申请日：2012-04-30

Applicant: Ruben B Montez ,  Robert F Steimle

Inventor： Ruben B Montez ,  Robert F Steimle

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L23/06

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L21/743 ,  H01L23/04 ,  H01L23/053 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16788 ,  H01L2924/00

Abstract: A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

Abstract translation: 一种键合半导体器件，包括支撑衬底，相对于所述支撑衬底的一侧定位的半导体器件，覆盖所述支撑衬底和所述器件的帽衬底，所述支撑衬底和所述帽衬底之间的玻璃料接合环，电 支撑基板和盖基板之间的导电环。 导电环在半导体器件周围形成内环，并且玻璃料接合环在半导体器件周围形成外部结合环。