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    Channel predictive behavior and fault analysis
    31.
    发明授权
    Channel predictive behavior and fault analysis 有权

    公开(公告)号：US11606152B2

    公开(公告)日：2023-03-14

    申请号：US17342316

    申请日：2021-06-08

    Applicant: Cisco Technology, Inc.

    Inventor： Amendra Koul ,  David Nozadze ,  Mike Sapozhnikov ,  Joel Goergen ,  Arnav Shailesh Shah

    IPC: H04B17/15 ,  H04B17/24 ,  H04B10/071

    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.

    High speed traceless interconnect
    32.
    发明授权
    High speed traceless interconnect 有权

    公开(公告)号：US11482802B2

    公开(公告)日：2022-10-25

    申请号：US17333925

    申请日：2021-05-28

    Applicant: Cisco Technology, Inc.

    Inventor： Jason Visneski ,  George Edward Curtis ,  Mike Sapozhnikov ,  Peter Gunadisastra ,  Joel Goergen

    IPC: H05K1/11 ,  H05K3/34 ,  H01R12/53 ,  H05K1/18

    Abstract: An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.

    Combined liquid and air cooling system for fail-safe operation of high power density ASIC devices
    34.
    发明授权
    Combined liquid and air cooling system for fail-safe operation of high power density ASIC devices 有权

    公开(公告)号：US11343945B2

    公开(公告)日：2022-05-24

    申请号：US16697463

    申请日：2019-11-27

    Applicant: Cisco Technology, Inc.

    Inventor： M. Baris Dogruoz ,  Joel Goergen

    IPC: H05K7/20 ,  H05K1/02

    Abstract: A combined liquid and air cooling system is provided over a printed circuit board (PCB) of an electronic device, where the PCB includes an integrated circuit package including an application specific integrated circuit (ASIC) die and a plurality of high bandwidth memory (HBM) modules located proximate the ASIC die, and the combined liquid and air cooling system includes a liquid cooling system located over the integrated circuit package and an air cooling system integrated with the liquid cooling system and a portion of the PCB. The system operates in a normal mode, where both liquid and air cooling systems provide cooling to components of the PCB, and a fail-safe mode, where the liquid cooling system is not operating (e.g., due to a detected condition) but the air cooling system operation is adjusted such that it provides sufficient cooling to PCB components which facilitates continuous operation of the electronic device.

    VIRTUALIZED CHASSIS WITH POWER-OVER-ETHERNET FOR NETWORKING APPLICATIONS
    36.
    发明申请
    VIRTUALIZED CHASSIS WITH POWER-OVER-ETHERNET FOR NETWORKING APPLICATIONS 审中-公开

    公开(公告)号：US20200274725A1

    公开(公告)日：2020-08-27

    申请号：US16861041

    申请日：2020-04-28

    Applicant: CISCO TECHNOLOGY, INC.

    Inventor： Paolo Sironi ,  Sushin Suresan Adackaconam ,  Joel Goergen ,  Roberto Gianella

    IPC: H04L12/10 ,  H01H83/22 ,  H02M1/32 ,  H01H83/10

    Abstract: An apparatus comprises an Ethernet port including high-side transformers and low-side transformers. High-side current paths supply high-side currents form a high voltage rail to high-side center taps of the high-side transformers. Low-side current paths supply or do not supply low-side currents from a low voltage rail to low-side center taps of the low-side transformers, and convert the low-side currents to sense voltages. A controller configures the low-side current paths to either supply or not supply the low-side currents to the low-side center taps when none of the sense voltages exceed a voltage threshold representative of an overcurrent threshold or when at least one of the sense voltages exceeds the voltage threshold, respectively. A current monitor injects additional current into the low-side current paths only when at least one of the high-side currents exceeds the overcurrent threshold.

    Stiffener ring combined with ASIC power delivery
    37.
    发明授权
    Stiffener ring combined with ASIC power delivery 有权

    公开(公告)号：US12142578B2

    公开(公告)日：2024-11-12

    申请号：US17492836

    申请日：2021-10-04

    Applicant: Cisco Technology, Inc.

    Inventor： Xiaohong Wu ,  Xing Wang ,  Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  Tomer Osi ,  Joel Goergen

    IPC: H01L23/50 ,  H01L23/00 ,  H01L23/053 ,  H01R12/00 ,  H05K1/18 ,  H05K7/10

    Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.

    Modular power supply architecture optimized for flat efficiency across loadings
    38.
    发明授权
    Modular power supply architecture optimized for flat efficiency across loadings 有权

    公开(公告)号：US11777394B1

    公开(公告)日：2023-10-03

    申请号：US17724985

    申请日：2022-04-20

    Applicant: Cisco Technology, Inc.

    Inventor： Xiqun Zhu ,  Sung Kee Baek ,  Joel Goergen ,  Doug Paul Arduini ,  Ruqi Li

    IPC: H02M1/00

    CPC classification number: H02M1/0048 ,  H02M1/0043

    Abstract: A control method improves the efficiency profile of a power supply across a wide range of output loading. The method includes obtaining a measure of output power for a power supply, which includes one or more output modules and an auxiliary power supply. The method determines whether a maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power. Responsive to a determination that the maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power, the controller of the power supply directs the auxiliary power supply to provide the output power.

    MULTIPLE SENSE POINTS FOR ADDRESSING A VOLTAGE GRADIENT
    40.
    发明申请
    MULTIPLE SENSE POINTS FOR ADDRESSING A VOLTAGE GRADIENT 有权

    公开(公告)号：US20220397599A1

    公开(公告)日：2022-12-15

    申请号：US17344539

    申请日：2021-06-10

    Applicant: Cisco Technology, Inc.

    Inventor： Jerrold Mark Pianin ,  Joel Goergen ,  Shobhana Ram Punjabi

    IPC: G01R31/28 ,  G05F1/625

    Abstract: Regulation of a voltage gradient may be provided. A plurality of test voltage values associated with a corresponding plurality of locations associated with an electronic device may be received. Then, based on the plurality of test voltage values, a target setpoint may be determined for a power supply that supplies power to the electronic device. The target setpoint may be configured to cause a maximum of voltage values at the plurality of locations to be below a maximum voltage level defined by a specification for the electronic device. The target setpoint may also be configured to cause a minimum of the voltage values at the plurality of locations to be above a minimum voltage level defined by the specification for the electronic device. The power supply may then be driven at the target setpoint.

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