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    Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
    31.
    发明授权
    Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion 有权
    形成具有六边形平面部分的一对电容器的基本组织单元的DRAM矩阵的方法

    公开(公告)号：US6156601A

    公开(公告)日：2000-12-05

    申请号：US333961

    申请日：1999-06-16

    Applicant: Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

    Inventor： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

    IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC classification number: H01L27/10844 ,  H01L27/10805

    Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

    Abstract translation: 动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。 每个电容器对具有第一电容器和其中的第二电容器之一。 每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

    Capacitor structure of semiconductor device for high dielectric constant
    32.
    发明授权
    Capacitor structure of semiconductor device for high dielectric constant 失效
    用于高介电常数的半导体器件的电容结构

    公开(公告)号：US6078093A

    公开(公告)日：2000-06-20

    申请号：US961070

    申请日：1997-10-30

    Applicant: Chang Jae Lee

    Inventor： Chang Jae Lee

    IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/00

    CPC classification number: H01L27/10852 ,  H01L28/40

    Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

    Abstract translation: 半导体器件电容器结构包括具有杂质扩散区域的半导体衬底; 绝缘层，其形成在所述半导体衬底上并且在所述杂质扩散区上具有接触孔; 沿所述接触孔的上边缘形成在所述绝缘膜上的半环型的第一下电极; 形成在通过接触孔露出的基板的表面上的第二下电极，接触孔的壁和第一下电极; 形成在第一和第二下部电极上的电介质层; 以及形成在电介质层上的上电极。 该结构增加了电容，从而提高了器件的特性和可靠性。

    Method of fabricating cmosfet
    33.
    发明授权
    Method of fabricating cmosfet 失效
    制造cmosfet的方法

    公开(公告)号：US5981320A

    公开(公告)日：1999-11-09

    申请号：US873716

    申请日：1997-06-12

    Applicant: Chang Jae Lee

    Inventor： Chang Jae Lee

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823835

    Abstract: A method of fabricating a CMOSFET includes the steps of selectively forming first and second conductive type wells in a semiconductor substrate, forming an isolation insulating layer at interface of the first and second conductive type wells, forming a first gate electrode formed of a first conductive type electrode over a predetermined area of the second conductive type well and a second gate electrode successively formed of a second conductive type electrode, a diffusion preventing layer, and the first conductive type electrode over a predetermined area of the first conductive type well, forming sidewall spacers on both sides of each of the first and second gate electrodes, forming second and first conductive type impurity regions under surfaces of the first and second conductive type wells, respectively, at both sides of the first and second gate electrodes and the their sidewall spacers, and forming a silicide layer on the first and second gate electrodes and on the semiconductor substrate where the first and second conductive type impurity regions are.

    Abstract translation: 制造CMOSFET的方法包括以下步骤：在半导体衬底中选择性地形成第一和第二导电类型的阱，在第一和第二导电类型的阱的界面处形成隔离绝缘层，形成由第一导电类型 电极在第二导电类型阱的预定区域上，以及第二栅电极，其在第一导电类型阱的预定区域上依次由第二导电类型电极，扩散防止层和第一导电类型电极形成，形成侧壁间隔物 在第一和第二栅极电极的两侧分别在第一和第二栅极电极及其侧壁间隔物的两侧分别在第一和第二导电类型阱的表面下形成第二和第一导电型杂质区， 以及在所述第一和第二栅极电极上以及所述半导体层上形成硅化物层 其中第一和第二导电类型杂质区域是位于其上。

    DRAM having a buried region contacted through a field region
    34.
    发明授权
    DRAM having a buried region contacted through a field region 失效
    DRAM具有通过场区域接触的掩埋区域

    公开(公告)号：US5663585A

    公开(公告)日：1997-09-02

    申请号：US524286

    申请日：1995-09-06

    Applicant: Chang Jae Lee ,  Oh Seok Han

    Inventor： Chang Jae Lee ,  Oh Seok Han

    IPC: H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L23/50

    CPC classification number: H01L27/10808

    Abstract: A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

    Abstract translation: 半导体存储单元具有半导体衬底，设置在半导体衬底上并具有两个杂质区的有源区，设置在有源区上的栅电极，与半导体衬底上的有源区隔离并具有收缩孔的场区， 设置在半导体衬底上的有源区域和场区上的电容器，以及设置在场区域下方的掩埋区域和通过接触孔与第一杂质区域接触的位线。

    Gas injector and film deposition apparatus having the same
    35.
    发明授权
    Gas injector and film deposition apparatus having the same 有权
    气体喷射器和具有该喷射器的成膜装置

    公开(公告)号：US08628621B2

    公开(公告)日：2014-01-14

    申请号：US12344489

    申请日：2008-12-27

    Applicant: Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

    Inventor： Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

    IPC: C23C16/00 ,  B05B1/24 ,  B05B1/00

    CPC classification number: C23C14/12 ,  C23C14/243 ,  C23C14/246 ,  C23C14/26

    Abstract: Provided are a gas injector and a film deposition apparatus having the same. The gas injector includes a body, a supply hole, an injection hole, and a distribution plate. The body is configured to provide an inner space therein. The supply hole is formed in an upper surface of the body to communicate with the inner space and receive a raw material. The injection hole is formed in a lower surface of the body to communicate with the inner space and inject the raw material. The distribution plate is disposed in the inner space of the body. A through hole is formed in the distribution plate. The distribution plate is disposed to be inclined at a predetermined angle with respect to a horizontal plane. The gas injector can uniformly inject the raw material and improve vaporization efficiency of the raw material having a powder form.

    Abstract translation: 提供了一种气体注入器和具有该气体注入器的成膜装置。 气体喷射器包括主体，供给孔，喷射孔和分配板。 身体构造成在其中提供内部空间。 供应孔形成在主体的上表面中以与内部空间连通并且接收原料。 注入孔形成在主体的下表面中，与内部空间连通并注入原料。 分配板设置在主体的内部空间中。 在分配板上形成通孔。 分配板相对于水平面倾斜预定角度。 气体喷射器可以均匀地注入原料并提高具有粉末形式的原料的蒸发效率。

    Gas injection unit and thin film deposition apparatus having the same
    36.
    发明授权
    Gas injection unit and thin film deposition apparatus having the same 有权
    气体注入单元和具有该气体注入单元的薄膜沉积设备

    公开(公告)号：US08317922B2

    公开(公告)日：2012-11-27

    申请号：US12344486

    申请日：2008-12-27

    Applicant: Chang Jae Lee ,  Young-Ho Kwon

    Inventor： Chang Jae Lee ,  Young-Ho Kwon

    IPC: C23C16/455 ,  C23C16/448 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

    CPC classification number: C23C14/12 ,  C23C14/243 ,  C23C14/246 ,  C23C14/26 ,  F28F13/003

    Abstract: A gas injection unit and a thin film deposition apparatus having the gas injection unit are provided. Since a variety of different kinds of organic materials can be sequentially vaporized and injected by a single injection unit, a variety of different kinds of thin films can be deposited in a single chamber. Furthermore, the gas injection structure of the injector unit can be easily controlled. Therefore, even when the process conditions such as the size of the substrate, the process temperature of the chamber, and the like are altered, it becomes possible to actively response to the altered process conditions by simply replacing some parts without replacing the whole injector unit.

    Abstract translation: 提供了具有气体注入单元的气体注入单元和薄膜沉积设备。 由于可以通过单个注射单元顺序地蒸发和注入各种不同种类的有机材料，所以可以在单个室中沉积各种不同种类的薄膜。 此外，可以容易地控制喷射器单元的气体注入结构。 因此，即使在基板的尺寸，室的处理温度等的处理条件发生变化的情况下，也可以通过简单地更换一些部件而不更换整个喷射器单元来主动地响应于改变的工艺条件 。

    Mobile broadband wireless access system for transferring service information during handover
    39.
    发明授权
    Mobile broadband wireless access system for transferring service information during handover 有权
    移动宽带无线接入系统，用于在切换期间传输业务信息

    公开(公告)号：US07873359B2

    公开(公告)日：2011-01-18

    申请号：US11072853

    申请日：2005-03-03

    Applicant: Chang Jae Lee ,  Young Suk Jin ,  Gi Seon Ryu

    Inventor： Chang Jae Lee ,  Young Suk Jin ,  Gi Seon Ryu

    IPC: H04W36/00 ,  H04W4/00

    CPC classification number: H04W36/26 ,  H04W92/20

    Abstract: The present invention is related to transmitting quality of service (QoS) information of a target base station for admitted service flows during a handover operation. The invention comprises providing a service to a mobile station from a serving base station and receiving at the serving base station a handover request from the mobile station. The serving base station the provides a handover notification to a target base station, wherein the handover notification comprises a QoS parameter associated with the service. The serving base station then receives from the target base station a handover notification response, wherein the handover notification response comprises service level prediction information that is determined in response to the QoS parameter associated with the service. Finally, the serving base station provides a handover response to the mobile station, the handover response comprising the service level prediction information.

    Abstract translation: 本发明涉及在切换操作期间发送目标基站的服务质量（QoS）信息以用于允许的服务流。 本发明包括从服务基站向移动台提供服务，并在服务基站处从移动台接收切换请求。 服务基站向目标基站提供切换通知，其中切换通知包括与服务相关联的QoS参数。 服务基站然后从目标基站接收切换通知响应，其中切换通知响应包括响应于与服务相关联的QoS参数确定的服务级别预测信息。 最后，服务基站向移动台提供切换响应，切换响应包括业务级预测信息。

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