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    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE FORMED IN AN EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATE
    31.
    发明申请
    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE FORMED IN AN EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATE 有权
    绝缘体（ETSOI）基板上的超薄半导体中嵌入的动态随机存取存储器件

    公开(公告)号：US20130146957A1

    公开(公告)日：2013-06-13

    申请号：US13316056

    申请日：2011-12-09

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/04 ,  H01L21/336

    CPC分类号： H01L27/1203 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

    摘要翻译： 一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。 电容器存在于沟槽的下部。 电介质垫片存在于沟槽上部的侧壁上。 介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。 导电材料填充物存在于沟槽的上部。 半导体器件存在于与沟槽相邻的SOI层上。 半导体器件通过导电材料填充与电容器电连通。

    Self-aligned strap for embedded capacitor and replacement gate devices
    33.
    发明授权
    Self-aligned strap for embedded capacitor and replacement gate devices 有权
    嵌入式电容器和更换栅极器件的自对准带

    公开(公告)号：US08492811B2

    公开(公告)日：2013-07-23

    申请号：US12886224

    申请日：2010-09-20

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

    摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

    SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES
    34.
    发明申请
    SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES 有权
    用于嵌入式电容器和替换栅极器件的自对准带

    公开(公告)号：US20120068237A1

    公开(公告)日：2012-03-22

    申请号：US12886224

    申请日：2010-09-20

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

    摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。