摘要:
A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
摘要:
Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
摘要:
An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要:
A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.
摘要:
The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.
摘要:
A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).
摘要:
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.