公开(公告)号：US06511881B1

公开(公告)日：2003-01-28

申请号：US10191722

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for fabricating split gate flash memory cell. The method includes sequentially forming conductive layers and insulating layers on a semiconductor substrate, followed by forming a first opening in the conductive layers and the insulating layers. Next, a shallow trench isolation is defined in the first opening and an insulating layer is defined simultaneously in the active area within the shallow trench isolation to form a first gate isolation layer. Then, a conductive sidewall layer is formed on the sidewalls of the first gate insulating layer. The first gate insulating layer and the conductive sidewall layer are used as a hard mask to remove the conductive layer not covered by the hard mask, thus forming a floating gate comprised of the conductive sidewall layer and the conductive layer underneath. A second gate insulating layer, control gate and source/drain are then formed conventionally.

Abstract translation: 一种用于制造分流栅闪存单元的方法。 该方法包括在半导体衬底上依次形成导电层和绝缘层，随后在导电层和绝缘层中形成第一开口。 接下来，在第一开口中限定浅沟槽隔离，并且在浅沟槽隔离中的有源区域中同时限定绝缘层，以形成第一栅极隔离层。 然后，在第一栅极绝缘层的侧壁上形成导电侧壁层。 第一栅绝缘层和导电侧壁层用作硬掩模以去除未被硬掩模覆盖的导电层，从而形成由导电侧壁层和下面的导电层组成的浮栅。 然后通常形成第二栅极绝缘层，控制栅极和源极/漏极。

公开(公告)号：US07056792B2

公开(公告)日：2006-06-06

申请号：US10819464

申请日：2004-04-06

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 堆叠式栅极闪存器件及其制造方法。 根据本发明的堆叠式栅极闪存器件的单元被布置在衬底内的单元沟槽中以实现存储单元的更高集成度。

公开(公告)号：US20050127422A1

公开(公告)日：2005-06-16

申请号：US10707396

申请日：2003-12-10

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract translation: 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US06870216B2

公开(公告)日：2005-03-22

申请号：US10606702

申请日：2003-06-26

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/72

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。

公开(公告)号：US06734686B2

公开(公告)日：2004-05-11

申请号：US10118778

申请日：2002-04-08

Applicant: Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

Inventor： Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

IPC: G01R2726

CPC classification number: G01F23/268 ,  G01F23/263 ,  G01F23/266 ,  G01N27/226

Abstract: This invention relates to a method for detecting quantity variation of high purity liquid chemicals by way of detecting capacitance variation to determine the liquid level of liquid chemicals. Meanwhile, the ratio of the area of the smallest electrode of the capacitor to the distance between the electrodes is adjusted to magnify the capacitance so that a very small variation can be observed clearly. This invention also discloses a device to carry out this method.

Abstract translation: 本发明涉及一种用于通过检测电容变化来检测高纯度液体化学品的量变化以确定液体化学品的液位的方法。 同时，电容器的最小电极的面积与电极之间的距离的比率被调节以放大电容，使得可以清楚地观察到非常小的变化。 本发明还公开了一种执行该方法的装置。

公开(公告)号：US06642116B2

公开(公告)日：2003-11-04

申请号：US10191108

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method of fabricating flash memory cell is described. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a buffer layer; removing portions of the buffer layer to farm a floating gate insulating layer; forming a second conductive layer; removing portions of the first conductive layer and the second conductive layer, such that the second conductive layer forms conductive spacers having conductive tips situated at the tips, and the floating gate insulating layer, the floating gate and the first gate insulating layer are combined as a floating gate region; forming a second insulating layer; forming a third conductive layer; removing portions of the third conductive layer and the second insulating layer to form a control gate, a second gate insulating layer, a first opening and a second opening; forming a source region on the substrate; forming spacers; and forming a drain region on the substrate.

Abstract translation: 描述了一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 形成第一导电层; 形成缓冲层; 去除所述缓冲层的部分以形成浮栅绝缘层; 形成第二导电层; 去除所述第一导电层和所述第二导电层的部分，使得所述第二导电层形成具有位于所述尖端处的导电尖端的导电间隔物，并且所述浮栅绝缘层，所述浮栅和所述第一栅极绝缘层被组合为 浮动栅区; 形成第二绝缘层; 形成第三导电层; 去除所述第三导电层和所述第二绝缘层的部分以形成控制栅极，第二栅极绝缘层，第一开口和第二开口; 在所述基板上形成源极区域; 形成间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US5989952A

公开(公告)日：1999-11-23

申请号：US934617

申请日：1997-09-22

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

IPC: C12Q1/48 ,  H01L21/02 ,  H01L21/8242 ,  H01L12/8242

CPC classification number: H01L28/92 ,  C12Q1/48 ,  H01L27/10852

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造具有冠型电容器的DRAM单元的方法。 该方法包括以下步骤：（a）在半导体衬底上形成晶体管; （b）在所述晶体管上形成绝缘层; （c）选择性地蚀刻绝缘层以形成接触开口; （d）在所述绝缘层上形成第一导电层并填充到所述接触开口中; （e）在所述第一导电层上形成蚀刻停止层和掩​​模层; （f）图案掩模层以形成多个开口; （g）在掩模层的侧壁上形成电介质间隔物，去除蚀刻停止层的暴露部分; （h）通过使用电介质间隔物作为掩模，各向异性地蚀刻掩模层和第一导电层，分别暴露蚀刻停止层和绝缘层; （i）去除未覆盖的蚀刻停止层以暴露第一导电层; （j）通过使用电介质间隔物作为掩模，将第一导电层各向异性蚀刻到预定深度，由此形成冠型存储电极; （k）去除电介质间隔物和蚀刻停止层; （l）在所述存储电极的暴露部分上形成介电层; 和（m）在所述电介质层上形成作为相对电极的第二导电层。

公开(公告)号：US07022573B2

公开(公告)日：2006-04-04

申请号：US10884701

申请日：2004-07-02

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。

公开(公告)号：US06998313B2

公开(公告)日：2006-02-14

申请号：US10733626

申请日：2003-12-11

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06753223B2

公开(公告)日：2004-06-22

申请号：US10295260

申请日：2002-11-15

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A method for fabricating a flash memory cell. The method starts with sequential formation of a first insulating layer, a first conductive layer and pad layer on a semiconductor substrate. Part of the pad layer is removed to form a first opening, followed by forming a conductive spacer, i.e. the tip, on the sidewalls of the first opening. Then, parts of the pad layer, first conductive layer, first insulating layer and substrate are removed to form a second opening. Next, a second insulating layer is formed to fill the first opening and the second opening to form a first gate insulating layer and shallow trench isolation. The first gate insulating layer is used as hard mask to remove part of the first conductive layer and the first insulating layer to form a floating gate and a second insulating layer. Tunneling oxide and control gate are then formed on the floating gate. Finally, a source/drain is formed.

Abstract translation: 一种制造闪存单元的方法。 该方法从在半导体衬底上顺序形成第一绝缘层，第一导电层和焊盘层开始。 去除衬垫层的一部分以形成第一开口，随后在第一开口的侧壁上形成导电间隔物，即尖端。 然后，去除衬垫层，第一导电层，第一绝缘层和衬底的一部分以形成第二开口。 接下来，形成第二绝缘层以填充第一开口和第二开口，以形成第一栅极绝缘层和浅沟槽隔离。 第一栅绝缘层用作硬掩模以去除部分第一导电层和第一绝缘层，以形成浮栅和第二绝缘层。 然后在浮动栅上形成隧道化氧化物和控制栅极。 最后，形成源极/漏极。