公开(公告)号：US20090300392A1

公开(公告)日：2009-12-03

申请号：US12505590

申请日：2009-07-20

申请人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

发明人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

IPC分类号： G06F1/32

CPC分类号： G06F1/325 ,  G06F1/3203 ,  G06F1/3209 ,  Y02D30/32 ,  Y02D50/20

摘要： A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.

摘要翻译： 计算机系统包括主处理器和网络接口，其中主处理器包括支持全功率模式，较低功率模式和掉电模式的资源，如标准系统总线规范（如PCI和InfiniBand）所示。 网络接口包括耦合到支持最小高速协议（例如千兆以太网或高速InfiniBand）的网络媒体的介质接口单元和诸如10Mb和100Mb以太网之一或较低速度的低速协议 InfiniBand。 响应于较低功率模式的事件信号输入，电源管理电路强制介质接口单元进入低速协议。 在较低功率模式下，执行低速协议时，网络接口消耗的功率小于指定功率，在执行高速协议时消耗大于指定功率。 网络接口中的逻辑工作在较低功耗模式，并使用较低速度协议来检测输入数据包中的模式。 响应于所述模式的检测，逻辑向主处理器发出复位信号。 因此，使用较低速度协议，网络接口作为较低功率模式的唤醒设备工作。

公开(公告)号：US06963921B1

公开(公告)日：2005-11-08

申请号：US09785015

申请日：2001-02-16

申请人： Li-Jau Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li Mou

发明人： Li-Jau Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： G06F15/16 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/12 ,  H04L69/161 ,  H04L69/163 ,  H04L69/166 ,  H04L69/22

摘要： A hardware packet accelerator parses incoming packets to retrieve header data for building a frame status and for verifying the incoming packets are part of an established connection with a host. The accelerator includes a connection database that allows retrieval of connection information based on an index constructed from a hashed TCP connection address. The frame status comprises information needed to perform packet re-assembly and is stored in a memory that is local (directly accessible) by a processing device that performs the packet re-assembly. Among other advantages, the processing device does not need to read packet header data from a packet buffer, saving large amounts of header data retrieval time.

摘要翻译： 硬件分组加速器解析输入分组以检索用于构建帧状态的头部数据，并且用于验证传入的分组是与主机建立的连接的一部分。 加速器包括连接数据库，其允许基于由散列TCP连接地址构建的索引检索连接信息。 帧状态包括执行分组重组所需的信息，并且被存储在由执行分组重组的处理设备本地（可直接访问）的存储器中。 除了其他优点之外，处理设备不需要从分组缓冲器读取分组报头数据，从而节省大量的报头数据检索时间。

公开(公告)号：US06556580B1

公开(公告)日：2003-04-29

申请号：US09465984

申请日：1999-12-16

申请人： Chi-Lie Wang ,  Lai-Chin Lo ,  Ngo Thanh Ho ,  Krishna Uppunda

发明人： Chi-Lie Wang ,  Lai-Chin Lo ,  Ngo Thanh Ho ,  Krishna Uppunda

IPC分类号： H04L1256

CPC分类号： H04L49/9063 ,  H04L12/12 ,  H04L47/50 ,  Y02D50/40

摘要： A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.

摘要翻译： 在网络接口卡（NIC）上使用发送分组缓冲器（TPB）来存储下载的分组，并将它们通过媒体接入控制器（MAC）和物理层接口（PHY）转发到线路上。 实现多功能TPB以允许该缓冲器的多次使用。 数据包可以通过多个源下载到此缓冲区。 不同类型的分组可以各自存储在预定义的位置。 例如，当TPB的后半部分用于传送保持活动或LAN报警时，上半部分可以用于将接收的分组与用于系统唤醒的唤醒模式进行比较。 通过多功能支持，可以更有效地实现各种PC管理功能，降低成本。

公开(公告)号：US09479464B1

公开(公告)日：2016-10-25

申请号：US12423690

申请日：2009-04-14

申请人： Chi-Lie Wang ,  BaoDong Hu ,  Scott W. Mitchell

发明人： Chi-Lie Wang ,  BaoDong Hu ,  Scott W. Mitchell

IPC分类号： H04L12/28 ,  H04L12/879 ,  H04L29/06 ,  H04L12/861

CPC分类号： H04L49/901 ,  H04L49/9042 ,  H04L49/9063 ,  H04L63/02 ,  H04L69/22

摘要： A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in to which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.

摘要翻译： 提供了适用于高速网络通信的数据处理系统，用于管理这种系统的网络接口和网络接口的方法，通过网络接收的分组的处理通过网络接口层的嵌入式逻辑来实现 。 网络接口上的传入数据包被解析和分类，因为它们存储在缓冲存储器中。 耦合到网络接口上的缓冲存储器的功能逻辑能够使用由解析和分类步骤产生的指针和分组分类信息在单个周期内访问分组内的任何数据字段。 在数据包从缓冲存储器传出之前，数据包中的数据字段的操作结果是可用的。 本发明还提供了一种数据处理系统，网络接口管理方法和网络接口，该系统包括在系统的网络接口层的嵌入式防火墙，可防止内部和外部对数据安全的攻击 处理系统。 此外，本发明提供了一种数据处理系统，网络接口管理方法和网络接口，其通过在网络接口级别应用优先级规则来支持从网络进入的分组的服务管理类别 系统。

公开(公告)号：US08332554B2

公开(公告)日：2012-12-11

申请号：US13172298

申请日：2011-06-29

申请人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

发明人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L29/06068 ,  H04L29/06 ,  H04L29/12254 ,  H04L61/2038 ,  H04L69/08 ,  H04L69/324

摘要： In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

摘要翻译： 在网络模块的一个实施例中，第一块接收串行数字媒体信号，并且基于串行数字媒体信号提供并行数字媒体信号。 与第一块操作的第二块将并行数字媒体信号存储在输出帧中的相应时隙中，并且响应于接收到的帧而发送输出帧。

公开(公告)号：US07996588B2

公开(公告)日：2011-08-09

申请号：US10449816

申请日：2003-05-30

申请人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

发明人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L29/06068 ,  H04L29/06 ,  H04L29/12254 ,  H04L61/2038 ,  H04L69/08 ,  H04L69/324

摘要： In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

摘要翻译： 在网络模块的一个实施例中，第一块接收串行数字媒体信号，并且基于串行数字媒体信号提供并行数字媒体信号。 与第一块操作的第二块将并行数字媒体信号存储在输出帧中的相应时隙中，并且响应于接收到的帧而发送输出帧。

公开(公告)号：US07860120B1

公开(公告)日：2010-12-28

申请号：US09916715

申请日：2001-07-27

申请人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

发明人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： H04L12/56

CPC分类号： H04L49/9052 ,  H04L47/6215 ,  H04L49/9005

摘要： A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities using dynamic buffer allocation. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities. Logic dynamically allocates the memory using a list of buffer descriptors for corresponding buffers in said memory. The list of buffer descriptors comprises a free buffer list and a used buffer list for each of the virtual paths served by the system. A used buffer descriptor is released from the used buffer list, after the data stored in the corresponding used buffer has been transmitted, to the free buffer list for a virtual path which has the largest amount traffic or which has the smallest number of free buffers in its free buffer list.

摘要翻译： 在主机端口和网络端口之间的网络接口中的多个虚拟路径根据各自的优先级使用动态缓冲器分配进行管理。 因此，通过单个物理网络端口支持多级服务质量。 在传输到网络之前，应用变体过程来处理已经下载到网络接口的分组。 网络接口还包括用作发送缓冲器的存储器，其将从主计算机接收的数据分组存储在第一端口上，并且向第二端口提供数据以在网络上传输。 网络接口中的控制电路将存储器作为具有各自优先级的多个先进先出FIFO队列进行管理。 根据与分组相关联的服务质量参数，逻辑将从主机处理器接收到的分组放置在多个FIFO队列中的一个中。 逻辑根据各自的优先级传输多个FIFO队列中的分组。 逻辑使用所述存储器中的相应缓冲器的缓冲器描述符列表动态地分配存储器。 缓冲器描述符的列表包括由系统服务的每个虚拟路径的空闲缓冲器列表和使用的缓冲器列表。 在使用缓冲区列表中释放已使用的缓冲区描述符后，将存储在相应的已用缓冲区中的数据发送到具有最大数量流量或具有最小数量的可用缓冲区的虚拟路径的空闲缓冲区列表中 其免费缓冲列表。

公开(公告)号：US07577857B1

公开(公告)日：2009-08-18

申请号：US09942789

申请日：2001-08-29

申请人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

发明人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

IPC分类号： G06F1/32

CPC分类号： G06F1/325 ,  G06F1/3203 ,  G06F1/3209 ,  Y02D30/32 ,  Y02D50/20

摘要： A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.

摘要翻译： 计算机系统包括主处理器和网络接口，其中主处理器包括支持全功率模式，较低功率模式和掉电模式的资源，如标准系统总线规范（如PCI和InfiniBand）所示。 网络接口包括耦合到支持最小高速协议（例如千兆以太网或高速InfiniBand）的网络媒体的介质接口单元和诸如10Mb和100Mb以太网之一或较低速度的低速协议 InfiniBand。 响应于较低功率模式的事件信号输入，电源管理电路强制介质接口单元进入低速协议。 在较低功率模式下，执行低速协议时，网络接口消耗的功率小于指定功率，在执行高速协议时消耗大于指定功率。 网络接口中的逻辑工作在较低功耗模式，并使用较低速度协议来检测输入数据包中的模式。 响应于所述模式的检测，逻辑向主处理器发出复位信号。 因此，使用较低速度协议，网络接口作为较低功率模式的唤醒设备工作。

公开(公告)号：US07003118B1

公开(公告)日：2006-02-21

申请号：US09723418

申请日：2000-11-27

申请人： Li-Jau (Steven) Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li (Karen) Mou

发明人： Li-Jau (Steven) Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li (Karen) Mou

IPC分类号： G06F15/16

CPC分类号： H04L63/0485 ,  H04L63/164

摘要： An architecture for a high performance IPSEC accelerator. The architecture includes components for scanning fields of packets, programming an IPSEC services device according to the scanned fields, and modifying the scanned packet with an output from the IPSEC security services device. Preferably, the architecture is implemented in hardware, and attached to a host machine. Hardware devices, fast in comparison to software processing and network speeds, allows the computationally intensive IPSEC processes to be completed in real-time and reduce or eliminate bottlenecks in the path of a packet being sent or received to/from a network.

摘要翻译： 高性能IPSEC加速器架构。 该架构包括用于扫描数据包的组件，根据扫描字段对IPSEC服务设备进行编程，以及使用IPSEC安全服务设备的输出修改扫描的数据包。 优选地，该架构以硬件实现，并且附接到主机。 与软件处理和网络速度相比，硬件设备能够快速完成计算密集型IPSEC流程，并减少或消除向/从网络发送或接收数据包的路径中的瓶颈。

公开(公告)号：US06385672B1

公开(公告)日：2002-05-07

申请号：US08879406

申请日：1997-06-20

申请人： Chi-Lie Wang ,  Richard S. Reid

发明人： Chi-Lie Wang ,  Richard S. Reid

IPC分类号： G06F1202

CPC分类号： H04L49/9089 ,  G06F5/14 ,  G06F2205/102 ,  G06F2205/108 ,  H04L49/90 ,  H04L49/901

摘要： The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned into separate transmit and receive buffers. This flexible partitioning allows the relative sizes of the transmit and receive buffers to be optimized across a wide range of buses, data networks and network usage patterns. The transmit and receive buffers are structured as ring buffers within respectively allocated portions of the buffer memory. The buffer memory is controlled by a simple finite state machine controller, which is free from the performance impediments and higher cost associated with a microprocessor-based controller. The present invention also provides support for retransmission of packets that encounter transmission problems such as collisions during transmissions on the data network. The present invention additionally provides the ability to discard incomplete packets.

摘要翻译： 本发明提供了一种通过在单个缓冲存储器中缓冲计算机系统和数据网络之间的传输中的数据来促进计算机系统和数据网络之间的通信的装置，其可以被灵活地划分成单独的发送和接收缓冲器。 这种灵活的分区允许在广泛的总线，数据网络和网络使用模式上优化发送和接收缓冲区的相对大小。 发送和接收缓冲器被构造为在缓冲存储器的分别分配的部分内的环形缓冲器。 缓冲存储器由简单的有限状态机控制器控制，其不受与基于微处理器的控制器相关的性能障碍和较高成本的限制。 本发明还提供对在数据网络上的传输期间遇到诸如冲突之类的传输问题的分组的重传的支持。 本发明另外提供丢弃不完整分组的能力。