公开(公告)号：US20060228843A1

公开(公告)日：2006-10-12

申请号：US10907677

申请日：2005-04-12

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US06391708B1

公开(公告)日：2002-05-21

申请号：US09178150

申请日：1998-10-23

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L21/31695 ,  H01L21/32139 ,  Y10S438/947

摘要： A method of manufacturing a DRAM capacitor comprises the steps of providing a semiconductor substrate having a source/drain region thereon, and then forming an insulating layer over the substrate. Next, a storage node opening that exposes the source/drain region is formed in the insulating layer, and then a conductive layer is formed above the storage node opening and the insulating layer. Thereafter, porous insulating material is deposited over the first conductive layer. The porous material includes porous oxide, NanoPorous Silica or Xerogel Sol-Gel, for example. Subsequently, the porous insulating layer is used as a mask to carry out a plasma-etching operation so that a portion of the conductive layer is etched away to form a plurality of long and narrow crevices. Hence, a fork-shaped conductive layer is formed. The fork-shaped first conductive layer serves as the lower electrode of a capacitor. Finally, the porous insulating layer is removed, and then the dielectric layer and the upper electrode of a capacitor are sequentially formed over the fork-shaped structure.

摘要翻译： 制造DRAM电容器的方法包括以下步骤：提供其上具有源极/漏极区域的半导体衬底，然后在衬底上形成绝缘层。 接下来，在绝缘层中形成露出源极/漏极区域的存储节点开口，然后在存储节点开口和绝缘层上方形成导电层。 此后，多孔绝缘材料沉积在第一导电层上。 多孔材料例如包括多孔氧化物，纳米多孔二氧化硅或Xerogel溶胶 - 凝胶。 随后，使用多孔绝缘层作为掩模进行等离子体蚀刻操作，使得导电层的一部分被蚀刻掉以形成多个长而窄的缝隙。 因此，形成叉形导电层。 叉形第一导电层用作电容器的下电极。 最后，去除多孔绝缘层，然后在叉形结构上依次形成电容器的电介质层和上电极。

公开(公告)号：US06294314B2

公开(公告)日：2001-09-25

申请号：US09076243

申请日：1998-05-11

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： G03F700

CPC分类号： G03F7/405 ,  G03F7/40

摘要： A method of fabricating an opening with a deep ultra-violet photoresist layer. An insulating layer is formed on a substrate having a device structure. A deep ultra-violet photoresist layer with a first opening is formed on the insulating layer and a hard mask layer is then formed on the surface and the sidewalls of the deep ultra-violet photoresist layer. The first opening is used to pattern the insulating layer to form a second opening within the insulating layer wherein the hard mask layer is to protect the deep ultra-violet photoresist layer. The deep ultra-violet photoresist layer and the hard mask layer are removed to expose the insulating layer and a desired opening is thus accomplished.

摘要翻译： 一种制造具有深紫外光致抗蚀剂层的开口的方法。 在具有器件结构的衬底上形成绝缘层。 在绝缘层上形成具有第一开口的深紫外光致抗蚀剂层，然后在深紫外光致抗蚀剂层的表面和侧壁上形成硬掩模层。 第一开口用于图案化绝缘层，以在绝缘层内形成第二开口，其中硬掩模层用于保护深紫外光致抗蚀剂层。 去除深紫外光致抗蚀剂层和硬掩模层以暴露绝缘层，从而实现所需的开口。

公开(公告)号：US06175135B1

公开(公告)日：2001-01-16

申请号：US09082658

申请日：1998-05-21

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78615

摘要： The structure in this present invention includes a substrate having a buried-in oxide layer near the surface of the substrate and a silicon surface layer of base over the buried-in oxide layer. After that the structure further includes a conductive layer of gate on the substrate, a dielectric layer on the conductive layer of gate, a metal plug penetrates through the conductive layer and the dielectric layer and reach down to the silicon surface layer but not through. The metal plug, the conductive layer of gate and the silicon surface of base are electrically coupled together.

摘要翻译： 本发明的结构包括在衬底的表面附近具有埋入氧化物层的衬底和在掩埋氧化物层上的基底的硅表面层。 之后，该结构还包括基板上的栅极导电层，栅极导电层上的电介质层，金属插塞穿过导电层和电介质层并到达硅表面层但不通过。 金属插塞，栅极的导电层和基底的硅表面电耦合在一起。

公开(公告)号：US06130011A

公开(公告)日：2000-10-10

申请号：US136553

申请日：1998-08-19

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： G03C5/00

CPC分类号： G03F7/405

摘要： A method of fabricating a deep UV implantation mask. A deep UV photo-resist layer is formed on a substrate. The deep UV photo-resist layer is defined to cover a part of the substrate. A silylation process is performed to transform the surface of the deep UV photo-resist layer into a hard mask layer. Using the hard mask layer as a mask, the substrate is implanted with ions.

摘要翻译： 一种制造深UV注入掩模的方法。 在基板上形成深紫外光致抗蚀剂层。 深UV光致抗蚀剂层被定义为覆盖基底的一部分。 进行甲硅烷基化处理以将深UV光致抗蚀剂层的表面转变成硬掩模层。 使用硬掩模层作为掩模，用离子注入衬底。

公开(公告)号：US6010943A

公开(公告)日：2000-01-04

申请号：US89248

申请日：1998-06-02

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A method of fabricating cylindrical capacitors comprising the steps of forming a gate and a source/drain region on a substrate, and then forming an insulating layer over the substrate. Next, a contact opening that exposes one of the source/drain regions is formed in the insulating layer. Subsequently, a first conductive layer is deposited over the insulating layer and into the contact opening, and then the first conductive layer is patterned. Thereafter, a first deep ultra-violet photoresist layer, a hard mask layer and a second deep ultra-violet photoresist layer are sequentially formed over the substrate structure. Next, the second deep ultra-violet photoresist layer is used as a mask to pattern the hard mask layer and the first deep ultra-violet photoresist layer. Ultimately, an opening that exposes a portion of the first conductive layer is formed. Then, the second deep ultra-violet photoresist layer is removed. After that, a silicon layer is formed on the sidewalls of the opening, and then the hard mask layer and the first deep ultra-violet photoresist layer are removed to expose the insulating layer and the silicon layer. The silicon layer and the first conductive layer together serve as the lower electrode of the capacitor. Finally, a dielectric layer and then a second conductive layer are sequentially formed over the lower electrode. The second conductive layer functions as the upper electrode of the capacitor.

摘要翻译： 一种制造圆柱形电容器的方法，包括以下步骤：在衬底上形成栅极和源极/漏极区域，然后在衬底上形成绝缘层。 接下来，在绝缘层中形成露出源/漏区之一的接触开口。 随后，在绝缘层上沉积第一导电层并进入接触开口，然后对第一导电层进行图案化。 此后，在衬底结构上依次形成第一深紫外光致抗蚀剂层，硬掩模层和第二深紫外光致抗蚀剂层。 接下来，使用第二深紫外光致抗蚀剂层作为掩模来对硬掩模层和第一深紫外光致抗蚀剂层进行图案化。 最终，形成露出第一导电层的一部分的开口。 然后，去除第二深紫外光致抗蚀剂层。 之后，在开口的侧壁上形成硅层，然后去除硬掩模层和第一深紫外光致抗蚀剂层，以露出绝缘层和硅层。 硅层和第一导电层一起用作电容器的下电极。 最后，在下电极上依次形成电介质层，然后第二导电层。 第二导电层用作电容器的上电极。

公开(公告)号：US6001716A

公开(公告)日：1999-12-14

申请号：US121154

申请日：1998-07-22

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/441

CPC分类号： H01L29/4966 ,  H01L21/28088

摘要： A method of fabricating a metal gate includes forming a gate insulating layer on a provided substrate, forming a PVD titanium nitride layer on the gate insulating layer, forming a CVD titanium nitride layer on the PVD titanium nitride layer, and forming a CVD tungsten layer on the CVD titanium nitride layer. The CVD tungsten layer, the CVD titanium nitride layer, and the PVD titanium nitride layer are later patterned to form the metal gate.

摘要翻译： 制造金属栅极的方法包括：在所提供的衬底上形成栅极绝缘层，在栅极绝缘层上形成PVD氮化钛层，在PVD氮化钛层上形成CVD氮化钛层，并在其上形成CVD钨层 CVD氮化钛层。 随后将CVD钨层，CVD氮化钛层和PVD氮化钛层图案化以形成金属栅极。

公开(公告)号：US07326622B2

公开(公告)日：2008-02-05

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US20060094195A1

公开(公告)日：2006-05-04

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US06350682B1

公开(公告)日：2002-02-26

申请号：US09073920

申请日：1998-05-06

申请人： Kuan-Yang Liao

发明人： Kuan-Yang Liao

IPC分类号： H01L214763

CPC分类号： H01L21/76813 ,  H01L21/76807

摘要： A method of fabricating dual damascene structure. A substrate having devices and a defined conductive layer is provided. A dielectric layer and a hard mask material layer are formed respectively over the substrate. An opening is defined within the hard mask material layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, a trench is formed within the dielectric layer by defining the hard material mask layer and a portion of dielectric layer until the conductive layer is exposed. The cross shape of the trench has a wider opening and a narrower bottom. A metal layer is then formed and the trench is filled up with the metal layer. The process of dual damascene structure is accomplished..

摘要翻译： 一种制造双镶嵌结构的方法。 提供具有器件和限定导电层的衬底。 分别在基板上形成介电层和硬掩模材料层。 在硬掩模材料层内限定开口。 由于硬掩模材料层和电介质层的选择性不同，通过限定硬质材料掩模层和电介质层的一部分直到导电层露出，在电介质层内形成沟槽。 沟槽的十字形状具有较宽的开口和较窄的底部。 然后形成金属层，并且用金属层填充沟槽。 双镶嵌结构的完成过程