公开(公告)号：US09117840B2

公开(公告)日：2015-08-25

申请号：US13399394

申请日：2012-02-17

申请人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US20100244153A1

公开(公告)日：2010-09-30

申请号：US12415021

申请日：2009-03-31

申请人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US07955964B2

公开(公告)日：2011-06-07

申请号：US12152380

申请日：2008-05-14

申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76883 ,  H01L21/76229

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。 该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

公开(公告)号：US20110227189A1

公开(公告)日：2011-09-22

申请号：US13151666

申请日：2011-06-02

申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L27/04

CPC分类号： H01L21/76883 ,  H01L21/76229

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。 该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

公开(公告)号：US09054025B2

公开(公告)日：2015-06-09

申请号：US12478135

申请日：2009-06-04

申请人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

发明人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

IPC分类号： H01L21/66 ,  H01L21/762

CPC分类号： H01L22/20 ,  H01L21/76224 ,  H01L22/12

摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

摘要翻译： 公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。 该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US07977181B2

公开(公告)日：2011-07-12

申请号：US12420254

申请日：2009-04-08

申请人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang

发明人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.

摘要翻译： 提供了一种方法，其包括分别在第一和第二区域中形成第一和第二栅极结构，第一栅极结构包括具有第一厚度的第一硬掩模层，第二栅极结构包括具有第二厚度的第二硬掩模层 从第二栅极结构去除第二硬掩模层，在第一和第二栅极结构上形成层间电介质（ILD），执行第一化学机械抛光（CMP），将硅层从 第二栅极结构，由此形成第一沟槽，形成第一金属层以填充第一沟槽，执行第二CMP，从第一栅极结构移除第一硬掩模层和硅层的剩余部分，从而形成第二沟槽， 形成第二金属层以填充第二沟槽，并执行第三CMP。

公开(公告)号：US07919792B2

公开(公告)日：2011-04-05

申请号：US12338632

申请日：2008-12-18

申请人： Oscar M. K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

发明人： Oscar M. K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

摘要翻译： 公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。 在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半 的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置，并且与所述第一标准单元间隔开第二间隔， 最小 其中所述第一和第二间距的总和至少与所述最小间隔一样大。 公开了一种形成标准的方法。

公开(公告)号：US20100112732A1

公开(公告)日：2010-05-06

申请号：US12478135

申请日：2009-06-04

申请人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

发明人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L21/76224 ,  H01L22/12

摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

摘要翻译： 公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。 该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

公开(公告)号：US20100052070A1

公开(公告)日：2010-03-04

申请号：US12536878

申请日：2009-08-06

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

摘要翻译： 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。