公开(公告)号：US09058284B1

公开(公告)日：2015-06-16

申请号：US13422979

申请日：2012-03-16

申请人： Amos Ben-Meir ,  John Gregory Favor

发明人： Amos Ben-Meir ,  John Gregory Favor

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/0855 ,  G06F12/1009 ,  G06F12/1027

摘要： Method and apparatus for performing table lookup are disclosed. In one embodiment, the method includes providing a lookup table, where the lookup table includes a plurality of translation modes and each translation mode includes a corresponding translation table tree supporting a plurality of page sizes. The method further includes receiving a search request from a requester, determining a translation table tree for conducting the search request, determining a lookup sequence based on the translation table tree, generating a search output using the lookup sequence, and transmitting the search output to the requester. The plurality of translation modes includes a first set of page sizes for 32-bit operating system software and a second set of page sizes for 64-bit operating system software. The plurality of page sizes includes non-global pages, global pages, and both non-global and global pages.

摘要翻译： 公开了用于执行表查找的方法和装置。 在一个实施例中，该方法包括提供查找表，其中查找表包括多个翻译模式，并且每个翻译模式包括支持多个页面大小的对应的翻译表格树。 该方法还包括从请求者接收搜索请求，确定用于进行搜索请求的翻译表格树，基于转换表格树确定查找序列，使用查找序列生成搜索输出，并将搜索输出发送到 请求者 多个翻译模式包括用于32位操作系统软件的第一组页面大小和用于64位操作系统软件的第二组页面大小。 多个页面大小包括非全局页面，全局页面以及非全局页面和全局页面。

公开(公告)号：US08051247B1

公开(公告)日：2011-11-01

申请号：US12030846

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3004 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

摘要： A circuit for tracking memory operations with trace-based execution is disclosed. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Executing one of the active memory operations updates a checkpoint location. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. After the trace is committed, all of the checkpoint entries associated with the trace are invalidated.

摘要翻译： 公开了一种用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 执行其中一个活动内存操作更新检查点位置。 在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。 轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。 提交跟踪后，与跟踪相关联的所有检查点条目都将失效。

公开(公告)号：US08015359B1

公开(公告)日：2011-09-06

申请号：US11782238

申请日：2007-07-24

申请人： John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Richard Thaik

发明人： John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Richard Thaik

IPC分类号： G06F13/00

CPC分类号： G06F12/0815 ,  G06F9/3017 ,  G06F9/322 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/3844 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1054 ,  Y02D10/13

摘要： An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.

摘要翻译： 公开了一种用于处理器的指令处理电路。 指令处理电路适于基于一个或多个指令序列向处理器的执行单元提供一个或多个操作序列。 所述指令处理电路包括至少一个高速缓存电路，并且所述处理电路包括定序器和耦合到所述定序器的页面翻译缓冲器，用于跟踪验证并维持存储器与所述至少一个高速缓存之间的一致性。

公开(公告)号：US07877630B1

公开(公告)日：2011-01-25

申请号：US12030852

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F9/3004 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3863 ,  G06F11/3648

摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

摘要翻译： 本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 跟踪中的所有操作执行完毕后，跟踪将以原子方式执行并成为合格的承诺。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 存储器操作排序条目对应于每个活动存储器操作。 回滚请求导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。

公开(公告)号：US07797517B1

公开(公告)日：2010-09-14

申请号：US11561274

申请日：2006-11-17

申请人： John Gregory Favor

发明人： John Gregory Favor

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/30094 ,  G06F9/30065 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/384

摘要： Reference architecture instructions are translated into target architecture operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, a trace is based on a plurality of basic blocks. In some embodiments, a trace is committed or aborted as a single entity. Sequences of operations are optimized by fusing collections of operations; fused operations specify a same observable function as respective collections, but advantageously enable more efficient processing. In some embodiments, a collection comprises multiple register operations. Fusing a register operation with a branch operation in a trace forms a fused reg-op/branch operation. In some embodiments, branch instructions translate into assert operations. Fusing an assert operation with another operation forms a fused assert operation. In some embodiments, fused operations only set architectural state, such as high-order portions of registers, that is subsequently read before being written.

摘要翻译： 参考架构指令被转换为目标架构操作。 在一些实施例中，以预测的执行顺序的操作顺序形成轨迹。 在一些实施例中，迹线基于多个基本块。 在一些实施例中，将跟踪作为单个实体提交或中止。 通过融合操作集合来优化操作顺序; 融合操作指定与相应集合相同的可观察函数，但有利地实现更有效的处理。 在一些实施例中，集合包括多个寄存器操作。 使用跟踪中的分支操作对寄存器操作进行融合，形成融合的操作/分支操作。 在一些实施例中，分支指令转换为断言操作。 将assert操作与另一个操作进行融合形成一个融合的assert操作。 在一些实施例中，融合操作仅设置架构状态，诸如寄存器的高阶部分，其随后在写入之前被读取。

公开(公告)号：US07681019B1

公开(公告)日：2010-03-16

申请号：US11561287

申请日：2006-11-17

申请人： John Gregory Favor

发明人： John Gregory Favor

IPC分类号： G06F9/455

CPC分类号： G06F9/4552

摘要： Reference architecture instructions are translated into target architecture operations. In some embodiments, an execution unit of a processor executes a function determined from a collection of operations, the function specifying functionality based on instructions, the collection selected from operations translated from the instructions. In further embodiments, the function is specified as a fused operation. Sequences of operations are optimized by fusing collections of operations; fused operations specify a same observable function as respective collections, but advantageously enable more efficient processing. In some embodiments, a collection comprises multiple register operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, fusing operations requires setting only final architectural state, such as final flag state; intermediate architectural state is used implicitly in a fused operation. In some embodiments, fused operations only set architectural state, such as high-order portions of registers, that is subsequently read before being written.

摘要翻译： 参考架构指令被转换为目标架构操作。 在一些实施例中，处理器的执行单元执行从操作集合确定的功能，基于指令的功能指定功能，从指令转换的操作中选择的集合。 在另外的实施例中，该功能被指定为融合操作。 通过融合操作集合来优化操作顺序; 融合操作指定与相应集合相同的可观察函数，但有利地实现更有效的处理。 在一些实施例中，集合包括多个寄存器操作。 在一些实施例中，以预测的执行顺序的操作顺序形成轨迹。 在一些实施例中，融合操作需要仅设置最终架构状态，例如最终标志状态; 中间架构状态被隐含地用于融合操作。 在一些实施例中，融合操作仅设置架构状态，诸如寄存器的高阶部分，其随后在写入之前被读取。

公开(公告)号：US06212629B1

公开(公告)日：2001-04-03

申请号：US09115165

申请日：1998-07-14

申请人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

发明人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

IPC分类号： G06F930

CPC分类号： G06F9/34 ,  G06F9/30003 ,  G06F9/30018 ,  G06F9/3005 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3555 ,  G06F9/38 ,  G06F9/3804 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3869 ,  G06F9/3885 ,  G06F11/364 ,  G06F11/3648 ,  G06F12/1027 ,  G06F12/145 ,  G06F15/8053

摘要： A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.

摘要翻译： 用于实现具有复杂指令集的虚拟架构的流水线控制系统在处理器中的RISC状半自主功能单元上分布。 解码器逻辑获取目标架构的指令，并将其转换为更简单的类似RISC的操作。 每个具有关联标签的这些操作被发布到功能单元。 地址处理单元计算指令和操作数的地址，执行段重定位，并管理处理器的存储器。 操作由单元以通常独立于其他单元的操作处理的方式执行。 这些单元将终止信息报告回解码器逻辑，但不能不可逆转地更改机器的状态。 基于终止信息，解码器逻辑依次退出正常终止的操作。 因此，功能单元能够以推测和无序的方式执行多个操作，以充分利用处理器的资源。

公开(公告)号：US6141673A

公开(公告)日：2000-10-31

申请号：US318671

申请日：1999-05-25

申请人： John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F17/14

CPC分类号： G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地中央处理单元（CPU）总线耦合到常规处理器。 MEU采用向量寄存器，向量算术逻辑单元（ALU）和操作数路由单元（ORU），以尽可能少的指令周期执行最大数量的多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US5682492A

公开(公告)日：1997-10-28

申请号：US380736

申请日：1995-01-30

申请人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

发明人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F11/36 ,  G06F15/78

CPC分类号： G06F11/3648 ,  G06F15/8053 ,  G06F9/30003 ,  G06F9/30018 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/34 ,  G06F9/3555 ,  G06F9/38 ,  G06F9/3804 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F9/3885

摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

摘要翻译： 流水线控制系统分布在处理器（10）中的功能单元（15,17,20,25）上。 解码器逻辑（12）向功能单元发出每个具有关联标签的操作，最多允许n个操作被显示。 单元执行操作并将终止信息报告回解码器逻辑，但不能不可逆转地改变机器的状态。 基于终止信息，解码器逻辑依次退出正常终止的操作。 如果操作异常终止，则解码器逻辑指示单元退出包括并晚于异常终止的操作的那些操作。

公开(公告)号：US09213643B2

公开(公告)日：2015-12-15

申请号：US13799268

申请日：2013-03-13

申请人： David Alan Kruckemyer ,  John Gregory Favor

发明人： David Alan Kruckemyer ,  John Gregory Favor

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F1/32

CPC分类号： G06F12/0833 ,  G06F1/3243 ,  G06F2212/1028 ,  Y02D10/13

摘要： Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

摘要翻译： 各个方面提供了实现高速缓存一致性协议。 系统包括至少一个处理部件和集中控制器。 所述至少一个处理组件包括高速缓存控制器。 高速缓存控制器被配置为管理与处理器相关联的高速缓冲存储器。 集中控制器被配置为基于处理器的功率状态与高速缓存控制器进行通信。