公开(公告)号：US20090303787A1

公开(公告)日：2009-12-10

申请号：US12134834

申请日：2008-06-06

申请人： Zhong Dong ,  Barbara Haselden

发明人： Zhong Dong ,  Barbara Haselden

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

摘要： In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

摘要翻译： 在具有电荷捕获电介质（150）的非易失性存储单元中，隧道电介质（140）包括邻近电荷捕获电介质的氯，而与电池的沟道区（120）相邻的氯不含氯（或更少的氯）。 与电荷捕获介质相邻的氯用于改善编程和/或擦除速度。 与通道区相邻的低氯浓度防止氯降解数据保留。 还提供其他功能。

公开(公告)号：US20090039413A1

公开(公告)日：2009-02-12

申请号：US12252571

申请日：2008-10-16

申请人： Zhong Dong ,  Chiliang Chen

发明人： Zhong Dong ,  Chiliang Chen

IPC分类号： H01L29/788

CPC分类号： H01L21/31662 ,  H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/02312 ,  H01L29/40114

摘要： Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated.

摘要翻译： 薄氧化膜生长在已经用气态或液态氯离子源处理过的硅上。 所得到的氧化物的厚度比在未处理的硅上获得的厚度更均匀，从而允许将给定的电荷存储在形成于所述氧化物上的浮栅上比未经处理的结构先前需要的时间更长的时间。

公开(公告)号：US07265015B2

公开(公告)日：2007-09-04

申请号：US11174081

申请日：2005-06-30

申请人： Zhong Dong ,  Tai-Peng Lee

发明人： Zhong Dong ,  Tai-Peng Lee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823481 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521

摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

公开(公告)号：US20070138579A1

公开(公告)日：2007-06-21

申请号：US11677768

申请日：2007-02-22

申请人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

发明人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

IPC分类号： H01L29/94

CPC分类号： H01L21/3144 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3145

摘要： Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.

摘要翻译： 氧化硅（210）在硅区（130）上生长。 与硅区域（130）相邻的氧化硅（210）的至少一部分（210 N）被氮化。 然后去除一些氧化硅（210），留下氮化部分（210N）。 另外的氧化硅在氮化硅氧化物部分（210N）下在硅区域（130）上热生长。 这种附加的氧化硅和氮化部分（210N）形成具有与氮区域相反的表面附近的高氮浓度的氧化硅层（140），而在其它地方具有低的氮浓度。 另一个氮化步骤增加邻近硅区域的氧化硅层（140）中的氮浓度，提供双峰氮分布。

公开(公告)号：US20090140318A1

公开(公告)日：2009-06-04

申请号：US11949596

申请日：2007-12-03

申请人： Zhong Dong

发明人： Zhong Dong

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L29/40117 ,  H01L29/513

摘要： In a nonvolatile memory, the tunnel dielectric (150) has a surface in physical contact with the charge trapping dielectric (160) and also has a surface in physical contact with a semiconductor region providing the active area (120, 130, 140). Under the vacuum level, the bottom edge of the conduction band of the tunnel dielectric (150) is higher at the surface contacting the charge-trapping dielectric (160) than at the surface contacting the active area.

摘要翻译： 在非易失性存储器中，隧道电介质（150）具有与电荷捕获电介质（160）物理接触的表面，并且还具有与提供有源区域（120,130,140）的半导体区域物理接触的表面。 在真空水平下，隧道电介质（150）的导带的底边缘在与电荷捕获电介质（160）接触的表面处比接触有源区的表面高。

公开(公告)号：US20070128800A1

公开(公告)日：2007-06-07

申请号：US11671740

申请日：2007-02-06

申请人： Zhong Dong ,  Tai-Peng Lee

发明人： Zhong Dong ,  Tai-Peng Lee

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

摘要翻译： 在衬底隔离沟槽（134）的蚀刻之前，将氯结合到在硅衬底（120）上形成的衬垫氧化物（110）中。 当在沟槽表面上热生长氧化硅衬垫（150.1）时，氯增强了沟槽的顶角（140℃）的倒圆。 通过CVD在第一衬垫（150.1）上沉积掺入氯的第二氧化硅衬垫（150.2），然后热生长第三衬里（150.3）。 控制第二衬套（150.2）中的氯浓度和三个衬垫（150.1,150.2,150.3）的厚度以改善拐角四舍五入，而不消耗太多的有效区域（140）。

公开(公告)号：US06524910B1

公开(公告)日：2003-02-25

申请号：US09670329

申请日：2000-09-27

申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

公开(公告)号：US07737487B2

公开(公告)日：2010-06-15

申请号：US12134834

申请日：2008-06-06

申请人： Zhong Dong ,  Barbara Haselden

发明人： Zhong Dong ,  Barbara Haselden

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

摘要： In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

摘要翻译： 在具有电荷捕获电介质（150）的非易失性存储单元中，隧道电介质（140）包括邻近电荷捕获电介质的氯，而与电池的沟道区（120）相邻的氯不含氯（或更少的氯）。 与电荷捕获介质相邻的氯用于改善编程和/或擦除速度。 与通道区相邻的低氯浓度防止氯降解数据保留。 还提供其他功能。

公开(公告)号：US20080135917A1

公开(公告)日：2008-06-12

申请号：US11608702

申请日：2006-12-08

申请人： Zhong Dong ,  Chiliang Chen

发明人： Zhong Dong ,  Chiliang Chen

IPC分类号： H01L29/788 ,  H01L21/31 ,  H01L23/58

CPC分类号： H01L21/31662 ,  H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/02312 ,  H01L29/40114

摘要： Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated.

摘要翻译： 薄氧化膜生长在已经用气态或液态氯离子源处理过的硅上。 所得到的氧化物的厚度比在未处理的硅上获得的厚度更均匀，从而允许将给定的电荷存储在形成于所述氧化物上的浮栅上比未经处理的结构先前需要的时间更长的时间。

公开(公告)号：US20070004136A1

公开(公告)日：2007-01-04

申请号：US11174081

申请日：2005-06-30

申请人： Zhong Dong ,  Tai-Peng Lee

发明人： Zhong Dong ,  Tai-Peng Lee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823481 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521

摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

摘要翻译： 在衬底隔离沟槽（134）的蚀刻之前，将氯结合到在硅衬底（120）上形成的衬垫氧化物（110）中。 当在沟槽表面上热生长氧化硅衬垫（150.1）时，氯增强了沟槽的顶角（140℃）的倒圆。 通过CVD在第一衬垫（150.1）上沉积掺入氯的第二氧化硅衬垫（150.2），然后热生长第三衬里（150.3）。 控制第二衬套（150.2）中的氯浓度和三个衬垫（150.1,150.2,150.3）的厚度以改善拐角四舍五入，而不消耗太多的有效区域（140）。