公开(公告)号：US12119218B2

公开(公告)日：2024-10-15

申请号：US17310303

申请日：2020-01-28

Applicant: Lam Research Corporation

Inventor： Stephen M. Sirard ,  Ratchana Limary ,  Yang Pan ,  Diane Hymes

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/67

CPC classification number: H01L21/02118 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/02348 ,  H01L21/30625 ,  H01L21/6715

Abstract: A method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by using stimuli selected from a group consisting of ultraviolet (UV) light and heat.

公开(公告)号：US20240194522A1

公开(公告)日：2024-06-13

申请号：US18586925

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US20230207384A1

公开(公告)日：2023-06-29

申请号：US18178948

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/4857 ,  H01L21/30604 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US09972695B2

公开(公告)日：2018-05-15

申请号：US15228160

申请日：2016-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ULVAC, Inc.

Inventor： Vijay Narayanan ,  Yohei Ogawa ,  John Rozen

IPC: H01L29/51 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/513 ,  H01L21/02043 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/02241 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28264 ,  H01L21/30612 ,  H01L29/0669 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7851

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

公开(公告)号：US09799554B2

公开(公告)日：2017-10-24

申请号：US15093834

申请日：2016-04-08

Applicant: SUSS MicroTec Lithography GmbH

Inventor： Katrin Fischer ,  Florian Palitschka ,  Darren Robert Southworth ,  William Whitney

IPC: H01L21/48 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/6715 ,  H01L21/76898

Abstract: A method for coating substrates provided with vias uses a first step in which the substrate is conditioned and a second step in which the substrate is coated with an electrically insulating material such that the vias are filled up completely.

公开(公告)号：US20170221704A1

公开(公告)日：2017-08-03

申请号：US15416645

申请日：2017-01-26

Applicant: Tokyo Electron Limited

Inventor： Nihar Mohanty ,  Lior Huli ,  Jeffrey Smith ,  Richard Farrell

IPC: H01L21/02 ,  C23C16/455

CPC classification number: H01L21/02359 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/0332

Abstract: Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

公开(公告)号：US09613808B1

公开(公告)日：2017-04-04

申请号：US15001094

申请日：2016-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/32139

Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.

公开(公告)号：US20160049471A1

公开(公告)日：2016-02-18

申请号：US14924273

申请日：2015-10-27

Applicant: Advanced Silicon Group, Inc.

Inventor： Brent A. Buchine ,  Marcie R. Black ,  Faris Modawar

IPC: H01L29/06 ,  H01L21/285 ,  H01L21/02 ,  H01L29/16 ,  H01L29/04 ,  H01M4/38 ,  H01L31/0352 ,  H01M4/134 ,  H01M4/04 ,  C23C14/34 ,  H01M4/36 ,  H01L21/3213 ,  H01L31/028

CPC classification number: H01L29/0669 ,  B01J20/10 ,  B01J20/28007 ,  B82Y20/00 ,  B82Y30/00 ,  C23C14/34 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/0234 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/32134 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/16 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/0352 ,  H01M4/0492 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/366 ,  H01M4/386 ,  H01M4/661 ,  H01M10/0525 ,  H01M2004/027 ,  Y02E10/50 ,  Y10S977/762

Abstract: A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Abstract translation: 用于蚀刻包括多晶硅以形成硅纳米结构的衬底的方法包括在衬底的顶部上沉积金属并使金属化衬底与包含约2至约49重量％的HF和氧化剂的蚀刻剂水溶液接触。

公开(公告)号：US20140057458A1

公开(公告)日：2014-02-27

申请号：US13840551

申请日：2013-03-15

Applicant: Geun Su Lee ,  SK HYNIX INC.

Inventor： Hyung Soon PARK ,  Kwon HONG ,  Jong Min LEE ,  Hyung Hwan KIM ,  Ji Hye HAN ,  Geun Su LEE

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/02343

Abstract: A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved.

Abstract translation: 公开了一种用于形成半导体器件的氧化硅膜的方法。 形成半导体器件的氧化硅膜的方法包括使用胺类化合物进行表面处理，从而可以提高氧化硅膜的均匀性和密度。

公开(公告)号：US08557672B2

公开(公告)日：2013-10-15

申请号：US13368206

申请日：2012-02-07

Applicant: Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

Inventor： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

IPC: H01L21/20

CPC classification number: H01L21/02183 ,  C23C16/308 ,  C23C16/45525 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31616 ,  H01L21/31637 ,  H01L28/60 ,  H01L28/65 ,  H01L29/518 ,  H01L29/7881

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.