公开(公告)号：US08107271B2

公开(公告)日：2012-01-31

申请号：US11649805

申请日：2007-01-05

申请人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

发明人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

IPC分类号： G11C5/06

CPC分类号： H03H7/38

摘要： A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

摘要翻译： 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。

公开(公告)号：US07495975B2

公开(公告)日：2009-02-24

申请号：US11377665

申请日：2006-03-17

申请人： Jae-Jun Lee ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Kwang-Soo Park

IPC分类号： G11C29/00

CPC分类号： G11C7/1051 ,  G11C5/14 ,  G11C7/1057 ,  H04L25/0278 ,  H04L25/0298

摘要： Provided is a memory system with an inductor. In the memory system, the inductor is connected to an on-die termination unit of a memory chip, thereby realizing constant gain characteristics without respect to a variation in an operating frequency. The inductor of the on-die termination unit may be embodied by connecting a wire bonding, a package line pattern, a PCB line pattern, a wire line, and/or an inductor device to pads of the memory chip.

摘要翻译： 提供了具有电感器的存储器系统。 在存储器系统中，电感器连接到存储器芯片的片上终端单元，从而实现恒定的增益特性而不考虑工作频率的变化。 可以通过将引线接合，封装线图案，PCB线图案，有线线路和/或电感器件连接到存储器芯片的焊盘来实现片上端接单元的电感器。

公开(公告)号：US07420818B2

公开(公告)日：2008-09-02

申请号：US11368654

申请日：2006-03-06

申请人： Kwang-Soo Park ,  Jae-Jun Lee

发明人： Kwang-Soo Park ,  Jae-Jun Lee

IPC分类号： H05K1/18

CPC分类号： G11C5/063 ,  G11C7/1048

摘要： A memory module includes: one or more semiconductor memory devices; a plurality of module tabs configured to transmit and receive signals between the one or more semiconductor memory devices and external devices; a data bus configured to transfer signals between data input/output pins of the one or more semiconductor memory devices and the plurality of module tabs; and impedance-matching capacitive elements, each coupled between a line of the data bus and a reference voltage. Accordingly, the memory module and a memory system employing such a module can achieve improved impedance matching, thereby also improving signal integrity.

摘要翻译： 存储器模块包括：一个或多个半导体存储器件; 多个模块突出部，被配置为在所述一个或多个半导体存储器件和外部装置之间传送和接收信号; 数据总线，被配置为在所述一个或多个半导体存储器件的数据输入/输出引脚与所述多个模块标签之间传送信号; 和阻抗匹配电容元件，每个耦合在数据总线的一行与参考电压之间。 因此，采用这种模块的存储器模块和存储器系统可以实现改进的阻抗匹配，从而也提高信号完整性。

公开(公告)号：US07350120B2

公开(公告)日：2008-03-25

申请号：US10833322

申请日：2004-04-28

申请人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

发明人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

IPC分类号： G11C29/00 ,  G01R31/02

CPC分类号： G11C29/48 ,  G11C2029/5602 ,  G11C2029/5606

摘要： A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.

摘要翻译： 缓冲存储器模块包括安装的缓冲电路和安装在板的第一表面上的多个存储器件，存储器件电连接到缓冲电路。 存储器模块还包括位于板的第二表面上并电连接到缓冲电路的多个测试焊盘。

公开(公告)号：US20070205848A1

公开(公告)日：2007-09-06

申请号：US11649805

申请日：2007-01-05

申请人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

发明人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

IPC分类号： H01P5/12 ,  H03H7/38

CPC分类号： H03H7/38

摘要： A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

摘要翻译： 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。

公开(公告)号：US07239216B2

公开(公告)日：2007-07-03

申请号：US10424923

申请日：2003-04-29

申请人： Myun-Joo Park ,  Jae-Jun Lee

发明人： Myun-Joo Park ,  Jae-Jun Lee

IPC分类号： H01P5/12

CPC分类号： H05K1/0216 ,  G11C7/1006 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09727 ,  H05K2201/09781

摘要： A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.

摘要翻译： 半导体存储器件包括具有存储器的存储器模块和将数据传送到存储器模块的数据总线，其中数据总线包括低频带数据传递单元，该单元去除数据的高频分量并将数据发送到 内存模块 低频带数据传送单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。 低频带数据传送单元包括并联连接到数据总线并形成为PCB图案的多个板。 低频带数据传送单元具有宽度宽的部分和宽度窄的部分交替连接的形状。 因此，在不添加单独的无源器件的情况下，半导体存储器件减少通过数据总线传送的数据的高频噪声，从而数据的电压裕度提高，诸如电容器等无源器件的成本降低，并且该过程 用于安装无源器件简化了。

公开(公告)号：US20070133247A1

公开(公告)日：2007-06-14

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20070030024A1

公开(公告)日：2007-02-08

申请号：US11377665

申请日：2006-03-17

申请人： Jae-Jun Lee ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Kwang-Soo Park

IPC分类号： H03K17/16

CPC分类号： G11C7/1051 ,  G11C5/14 ,  G11C7/1057 ,  H04L25/0278 ,  H04L25/0298

摘要： Provided is a memory system with an inductor. In the memory system, the inductor is connected to an on-die termination unit of a memory chip, thereby realizing constant gain characteristics without respect to a variation in an operating frequency. The inductor of the on-die termination unit may be embodied by connecting a wire bonding, a package line pattern, a PCB line pattern, a wire line, and/or an inductor device to pads of the memory chip.

摘要翻译： 提供了具有电感器的存储器系统。 在存储器系统中，电感器连接到存储器芯片的片上终端单元，从而实现恒定的增益特性而不考虑工作频率的变化。 可以通过将引线接合，封装线图案，PCB线图案，有线线路和/或电感器件连接到存储器芯片的焊盘来实现片上端接单元的电感器。

公开(公告)号：US20060245229A1

公开(公告)日：2006-11-02

申请号：US11368654

申请日：2006-03-06

申请人： Kwang-Soo Park ,  Jae-Jun Lee

发明人： Kwang-Soo Park ,  Jae-Jun Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C7/1048

摘要： A memory module includes: one or more semiconductor memory devices; a plurality of module tabs configured to transmit and receive signals between the one or more semiconductor memory devices and external devices; a data bus configured to transfer signals between data input/output pins of the one or more semiconductor memory devices and the plurality of module tabs; and impedance-matching capacitive elements, each coupled between a line of the data bus and a reference voltage. Accordingly, the memory module and a memory system employing such a module can achieve improved impedance matching, thereby also improving signal integrity.

摘要翻译： 存储器模块包括：一个或多个半导体存储器件; 多个模块突出部，被配置为在所述一个或多个半导体存储器件和外部装置之间发送和接收信号; 数据总线，被配置为在所述一个或多个半导体存储器件的数据输入/输出引脚与所述多个模块标签之间传送信号; 和阻抗匹配电容元件，每个耦合在数据总线的一行与参考电压之间。 因此，采用这种模块的存储器模块和存储器系统可以实现改进的阻抗匹配，从而也提高信号完整性。

公开(公告)号：US07106613B2

公开(公告)日：2006-09-12

申请号：US11064671

申请日：2005-02-24

申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。