公开(公告)号：US6074905A

公开(公告)日：2000-06-13

申请号：US222285

申请日：1998-12-28

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/66575 ,  H01L21/31111 ,  H01L21/823835 ,  H01L29/665

Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.

Abstract translation: 在光刻期间使用SiON抗反射涂层形成多晶硅线的新方法，其中在蚀刻之后在多晶硅侧壁和有源区表面上形成薄氧化物保护层以防止在集成电路的制造中由于SiON的去除而引起的损坏。 实现了 在硅衬底的表面上设置栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积SiON抗反射涂层。 在SiON抗反射涂层上形成光致抗蚀剂掩模。 SiON抗反射涂层，多晶硅层和栅极氧化物层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖以形成多晶硅线。 多晶硅线路和硅衬底被氧化以在多晶硅线路的侧壁和硅衬底的表面上形成保护氧化物层。 去除SiON抗反射涂层，其中保护性氧化物层保护多晶硅线和硅衬底免于在集成电路器件的制造中完全制造多晶硅线。

公开(公告)号：US08389316B2

公开(公告)日：2013-03-05

申请号：US13089765

申请日：2011-04-19

Applicant: Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

Inventor： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC: H01L21/00

CPC classification number: H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract translation: 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US08227869B2

公开(公告)日：2012-07-24

申请号：US13284594

申请日：2011-10-28

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/76

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

Abstract translation: 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。

公开(公告)号：US08122394B2

公开(公告)日：2012-02-21

申请号：US12212088

申请日：2008-09-17

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: G06F17/50 ,  G06F7/66 ,  G06K9/00 ,  H01L21/66

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

Abstract translation: 用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。 可以使用第二区域的图案来形成掩模。

公开(公告)号：US20110230002A1

公开(公告)日：2011-09-22

申请号：US12726215

申请日：2010-03-17

Applicant: Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

Inventor： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC: H01L21/26

CPC classification number: H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

Abstract translation: 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入到硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

公开(公告)号：US20110195554A1

公开(公告)日：2011-08-11

申请号：US13089765

申请日：2011-04-19

Applicant: Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

Inventor： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract translation: 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US20100065913A1

公开(公告)日：2010-03-18

申请号：US12212088

申请日：2008-09-17

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: H01L27/092 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

Abstract translation: 用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。 可以使用第二区域的图案来形成掩模。

公开(公告)号：US06207538B1

公开(公告)日：2001-03-27

申请号：US09472998

申请日：1999-12-28

Applicant: Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

Inventor： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

IPC: H01L2104

CPC classification number: H01L21/823892

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.

Abstract translation: 一种使用单一光刻掩模步骤，非保形氧化物层和化学机械抛光步骤在半导体衬底中形成n阱和p阱的方法。 在半导体基板上形成荧光体层。 在屏幕氧化物层上形成阻挡层。 阻挡层被图案化以在衬底的形成第一阱的区域上的阻挡层中形成第一开口。 我们将第一导电类型的杂质植入衬底中以形成第一孔。 在关键步骤中，在第一阱区和阻挡层上形成非共形氧化物层。 使用HDPCVD工艺形成的非共形氧化物层是至关重要的。 非保形氧化物层在阻挡层处被化学机械抛光停止。 使用选择性蚀刻去除阻挡层，以在剩余的非保形氧化物层中在衬底中将形成第二阱的区域上形成第二开口。 使用剩余的非保形氧化物作为掩模，我们通过第二开口植入第二导电类型的杂质以形成第二孔。 去除剩余的非保形氧化物层和屏幕氧化物层。

公开(公告)号：US6080638A

公开(公告)日：2000-06-27

申请号：US244880

申请日：1999-02-05

Applicant: Chung-Te Lin ,  Shwangming Jeng ,  Yuan-Horng Chiu ,  Kong-Beng Thei

Inventor： Chung-Te Lin ,  Shwangming Jeng ,  Yuan-Horng Chiu ,  Kong-Beng Thei

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method to reduce to reduce DRAM capacitor STI junction leakage current. A Shallow Trench Isolation opening is formed, within this opening Field Oxide is deposited. The top surface of the FOX is etched down and a second layer of oxide is deposited over the FOX and the adjacent active regions. This second layer of oxide is etched bringing the top surface down to below the level of the top surface of the surrounding active areas but leaving spacers where the top surface of the FOX intersects with the active areas.

Abstract translation: 一种降低DRAM电容器STI结的漏电流的方法。 形成浅沟槽隔离开口，在该开口中形成场氧化物。 FOX的顶表面被蚀刻并且在FOX和相邻的活性区上沉积第二层氧化物。 该第二层氧化物被蚀刻，使顶部表面向下降到低于周围有效区域的顶表面的水平面，但留下FOX的顶部表面与活性区域相交的间隔物。