公开(公告)号：US06207538B1

公开(公告)日：2001-03-27

申请号：US09472998

申请日：1999-12-28

申请人： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

发明人： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

IPC分类号： H01L2104

CPC分类号： H01L21/823892

摘要： A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.

摘要翻译： 一种使用单一光刻掩模步骤，非保形氧化物层和化学机械抛光步骤在半导体衬底中形成n阱和p阱的方法。 在半导体基板上形成荧光体层。 在屏幕氧化物层上形成阻挡层。 阻挡层被图案化以在衬底的形成第一阱的区域上的阻挡层中形成第一开口。 我们将第一导电类型的杂质植入衬底中以形成第一孔。 在关键步骤中，在第一阱区和阻挡层上形成非共形氧化物层。 使用HDPCVD工艺形成的非共形氧化物层是至关重要的。 非保形氧化物层在阻挡层处被化学机械抛光停止。 使用选择性蚀刻去除阻挡层，以在剩余的非保形氧化物层中在衬底中将形成第二阱的区域上形成第二开口。 使用剩余的非保形氧化物作为掩模，我们通过第二开口植入第二导电类型的杂质以形成第二孔。 去除剩余的非保形氧化物层和屏幕氧化物层。

公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC分类号： H01L21326

CPC分类号： H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

摘要翻译： 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US6074905A

公开(公告)日：2000-06-13

申请号：US222285

申请日：1998-12-28

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/31111 ,  H01L21/823835 ,  H01L29/665

摘要： A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.

摘要翻译： 在光刻期间使用SiON抗反射涂层形成多晶硅线的新方法，其中在蚀刻之后在多晶硅侧壁和有源区表面上形成薄氧化物保护层以防止在集成电路的制造中由于SiON的去除而引起的损坏。 实现了 在硅衬底的表面上设置栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积SiON抗反射涂层。 在SiON抗反射涂层上形成光致抗蚀剂掩模。 SiON抗反射涂层，多晶硅层和栅极氧化物层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖以形成多晶硅线。 多晶硅线路和硅衬底被氧化以在多晶硅线路的侧壁和硅衬底的表面上形成保护氧化物层。 去除SiON抗反射涂层，其中保护性氧化物层保护多晶硅线和硅衬底免于在集成电路器件的制造中完全制造多晶硅线。

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06790756B2

公开(公告)日：2004-09-14

申请号：US10385954

申请日：2003-03-11

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

IPC分类号： H01L213205

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06287926B1

公开(公告)日：2001-09-11

申请号：US09253297

申请日：1999-02-19

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US09123558B2

公开(公告)日：2015-09-01

申请号：US13164744

申请日：2011-06-20

申请人： Sheng-Hung Fan ,  Chu-Wei Hu ,  Chien-Chih Lin ,  Chih-Chung Chiu ,  Zheng Zeng ,  Wei-Li Tsao

发明人： Sheng-Hung Fan ,  Chu-Wei Hu ,  Chien-Chih Lin ,  Chih-Chung Chiu ,  Zheng Zeng ,  Wei-Li Tsao

IPC分类号： H01L29/73 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732

CPC分类号： H01L29/0692 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/732

摘要： In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.

摘要翻译： 根据一个实施例，本发明提供一种包括发射极区域的双极结型晶体管; 基地区 在发射极区域和基极区域之间的第一隔离; 在所述第一隔离区域上的栅极并且与所述发射极区域的周边的至少一部分重叠; 收集区域 以及在基极区域和集电极区域之间的第二隔离。

公开(公告)号：US06787470B2

公开(公告)日：2004-09-07

申请号：US10150300

申请日：2002-05-17

申请人： Chu-Wei Hu ,  Tsu Shih ,  Chen Cheng Chou

发明人： Chu-Wei Hu ,  Tsu Shih ,  Chen Cheng Chou

IPC分类号： H01L21302

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  Y10S438/959

摘要： A sacrificial semiconductor feature for preventing corrosion that can result during chemical-mechanical planarization (CMP) is disclosed. A semiconductor device of the invention is fabricated at least in part by performing CMP. The device includes a desired semiconductor feature and a sacrificial semiconductor feature. The desired semiconductor feature may have an unbalanced geometric pattern that includes a metallic line ending in at least one tip. The at least one tip is susceptible to corrosion resulting from performing CMP. The sacrificial semiconductor feature is preferably located off the metallic line of the desired semiconductor feature. The sacrificial semiconductor feature attracts charge induced during CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature. The presence of the sacrificial semiconductor feature thus substantially prevents corrosion of the desired semiconductor feature, including its tip(s).

摘要翻译： 公开了一种用于防止在化学机械平面化（CMP）期间可能产生的腐蚀的牺牲半导体特征。 至少部分地通过执行CMP来制造本发明的半导体器件。 该器件包括期望的半导体特征和牺牲半导体特征。 期望的半导体特征可以具有不平衡几何图案，其包括终止于至少一个尖端的金属线。 至少一个尖端容易受到执行CMP的腐蚀。 牺牲半导体特征优选地位于期望的半导体特征的金属线之外。 牺牲半导体特征吸引由CMP期望的半导体特征的至少一个尖端吸引的电荷。 因此牺牲半导体特征的存在基本上防止了期望的半导体特征（包括其尖端）的腐蚀。

公开(公告)号：US08932937B2

公开(公告)日：2015-01-13

申请号：US10151442

申请日：2002-05-20

申请人： Chu-Sheng Lee ,  Hsin-Chi Chen ,  Chu-Wei Hu

发明人： Chu-Sheng Lee ,  Hsin-Chi Chen ,  Chu-Wei Hu

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.

公开(公告)号：US06211069B1

公开(公告)日：2001-04-03

申请号：US09312601

申请日：1999-05-17

申请人： Chu-Wei Hu ,  Jiue Wen Weng ,  Ruey Yun Shiue

发明人： Chu-Wei Hu ,  Jiue Wen Weng ,  Ruey Yun Shiue

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76813

摘要： A process for forming a dual damascene opening, in a composite insulator layer, comprised of an overlying, wide diameter opening, used to accommodate a metal interconnect structure, and comprised of an underlying, narrow diameter opening, used to accommodate a metal via structure, has been developed. The process features the use of conventional photolithographic and anisotropic dry etching procedures, used to create an initial dual damascene opening, in the composite insulator layer. The subsequent formation of insulator spacers, on the vertical sides of the initial dual damascene opening, however, results in a final dual damascene opening, featuring a diameter smaller than the diameter displayed with the initial dual damascene opening.

摘要翻译： 一种在复合绝缘体层中形成双镶嵌开口的方法，包括用于容纳金属互连结构的上覆的宽直径开口，并且包括用于容纳金属通孔结构的下面的窄直径的开口， 已经开发。 该方法的特征在于在复合绝缘体层中使用常规光刻和各向异性干蚀刻方法，用于产生初始的双镶嵌开口。 然而，在初始双镶嵌开口的垂直侧面上随后形成绝缘体间隔件，导致最终的双镶嵌开口，其直径小于初始双镶嵌开口所显示的直径。