公开(公告)号：US10789540B2

公开(公告)日：2020-09-29

申请号：US15487295

申请日：2017-04-13

Applicant: D-Wave Systems Inc.

Inventor： Andrew D. King ,  Robert B. Israel ,  Paul I. Bunyk ,  Kelly T. R. Boothby ,  Steven P. Reinhardt ,  Aidan P. Roy ,  James A. King ,  Trevor M. Lanting ,  Abraham J. Evert

IPC: G06N10/00 ,  G06N3/12

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

公开(公告)号：US10671937B2

公开(公告)日：2020-06-02

申请号：US16308314

申请日：2017-06-07

Applicant: Sheir Yarkoni ,  D-WAVE SYSTEMS INC.

Inventor： Sheir Yarkoni ,  Trevor Michael Lanting ,  Kelly T. R. Boothby ,  Andrew Douglas King ,  Evgeny A. Andriyash ,  Mohammad H. Amin

IPC: G06N10/00 ,  B82Y10/00 ,  G06N7/08 ,  G06N3/04

Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

公开(公告)号：US20190266510A1

公开(公告)日：2019-08-29

申请号：US16308314

申请日：2017-06-07

Applicant: Sheir YARKONI ,  D-WAVE SYSTEMS INC.

Inventor： Sheir Yarkoni ,  Trevor Michael Lanting ,  Kelly T. R. Boothby ,  Andrew Douglas King ,  Evgeny A. Andriyash ,  Mohammad H. Amin

IPC: G06N10/00 ,  G06N7/08 ,  B82Y10/00

Abstract: A hybrid computer for generating samples employs a digital computer operable to perform post-processing. An analog computer may be communicatively coupled to the digital computer. The analog computer may be operable to return one or more samples corresponding to low-energy configurations of a Hamiltonian. Methods of generating samples from a quantum Boltzmann distribution to train a Quantum Boltzmann Machine, and from a classical Boltzmann distribution to train a Restricted Boltzmann Machine, are also taught. Computational systems and methods permit processing problems having size and/or connectivity greater than, and/or at least not fully provided by, a working graph of an analog processor. The approach may include determining preparatory biases toward a first classical spin configuration, evolving the analog processor in a first direction; evolving the analog processor in a second direction and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

公开(公告)号：US20250005418A1

公开(公告)日：2025-01-02

申请号：US18710133

申请日：2022-11-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Kelly T. R. Boothby ,  Min Jan Tsai ,  Berta Trullas Clavera ,  Mauricio Reis Filho ,  Paul I. Bunyk

IPC: G06N10/40

Abstract: A superconducting flux qubit readout system may include an input-output system connected to at least one shift register, the shift register comprising a first set, a second set, and a third set of shift register stages arranged in series, the first set of shift register stages coupled to a first set of qubits by a first plurality of latches, and the second set of shift register stages coupled to a second set of qubits by a second plurality of latches. Reading out states of a first set of qubits may include: shifting qubit state information to first holding latches communicatively coupled to a shift register; obtaining, by each shift register stage of the first set of shift register stages, state information from the first holding latches; and, propagating information along the shift register.

公开(公告)号：US12033996B2

公开(公告)日：2024-07-09

申请号：US17026740

申请日：2020-09-21

Applicant: D-Wave Systems Inc.

Inventor： Kelly T. R. Boothby

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H05K1/181 ,  H05K1/182 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/17155 ,  H01L2224/17505 ,  H01L2224/81815 ,  H05K2201/09072 ,  H05K2201/1053 ,  H05K2201/10537

Abstract: This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.

公开(公告)号：US20240118797A1

公开(公告)日：2024-04-11

申请号：US18205379

申请日：2023-06-02

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Fiona L. Hanington ,  Alexander Condello ,  William W. Bernoudy ,  Melody C. Wong ,  Aidan P. Roy ,  Kelly T. R. Boothby ,  Edward D. Dahl

IPC: G06F3/04847 ,  G06F3/04817 ,  G06F16/901 ,  G06N10/00 ,  G06T11/20

CPC classification number: G06F3/04847 ,  G06F3/04817 ,  G06F16/9024 ,  G06N10/00 ,  G06T11/206 ,  G06T2200/24

Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.

公开(公告)号：US11704586B2

公开(公告)日：2023-07-18

申请号：US17739411

申请日：2022-05-09

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Aidan P. Roy ,  Fabian A. Chudak ,  Zhengbing Bian ,  William G. Macready ,  Robert B. Israel ,  Kelly T. R. Boothby ,  Sheir Yarkoni ,  Yanbo Xue ,  Dmytro Korenkevych

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

公开(公告)号：US11704012B2

公开(公告)日：2023-07-18

申请号：US17855095

申请日：2022-06-30

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Fiona L. Hanington ,  Alexander Condello ,  William W. Bernoudy ,  Melody C. Wong ,  Aidan P. Roy ,  Kelly T. R. Boothby ,  Edward D. Dahl

IPC: G06F3/048 ,  G06F3/04847 ,  G06N10/00 ,  G06T11/20 ,  G06F3/04817 ,  G06F16/901

CPC classification number: G06F3/04847 ,  G06F3/04817 ,  G06F16/9024 ,  G06N10/00 ,  G06T11/206 ,  G06T2200/24

Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.

公开(公告)号：US11593695B2

公开(公告)日：2023-02-28

申请号：US16830650

申请日：2020-03-26

Applicant: D-WAVE SYSTEMS INC.

Inventor： William W. Bernoudy ,  Mohammad H. Amin ,  James A. King ,  Jeremy P. Hilton ,  Richard G. Harris ,  Andrew J. Berkley ,  Kelly T. R. Boothby

IPC: G06F17/00 ,  G06N10/00 ,  G06N10/60 ,  G06F15/16 ,  G06F17/10 ,  G06N10/40 ,  H03K19/00

Abstract: A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.

公开(公告)号：US11494683B2

公开(公告)日：2022-11-08

申请号：US16955526

申请日：2018-12-19

Applicant: D-Wave Systems Inc.

Inventor： Mohammad H. Amin ,  Paul I. Bunyk ,  Trevor M. Lanting ,  Chunqing Deng ,  Anatoly Smirnov ,  Kelly T. R. Boothby ,  Emile M. Hoskinson ,  Christopher B. Rich

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22

Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).