公开(公告)号：US20050088244A1

公开(公告)日：2005-04-28

申请号：US10693031

申请日：2003-10-23

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： H03B5/08 ,  H03L7/00 ,  H03L7/085 ,  H03L7/093 ,  H03L7/107 ,  H03L7/18

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/1075 ,  H03L7/18

摘要： Disclosed is a PLL (Phase Lock Loop) reducing the lock-in-time of the phase lock loop by altering the impedance of the damping resistor portion of the included LPF (Low Pass Filter) as a function of the difference in frequency or phase between a PLL applied reference frequency and the output frequency provided by the VCO (Voltage Controlled Oscillator) portion of the PLL. This variable impedance is accomplished by introducing a feed forward path that switches a capacitor in and out of the circuit in accordance with the difference frequency. One embodiment uses a mixer to provide the difference frequency signal.

公开(公告)号：US20070271051A1

公开(公告)日：2007-11-22

申请号：US11383570

申请日：2006-05-16

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R29/02 ,  G01R25/00

CPC分类号： G01R29/02 ,  G01R31/31725 ,  G01R31/31726

摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

摘要翻译： 所公开的方法和装置测量时钟信号的占空比。 可变占空比电路从时钟信号发生器接收时钟信号。 可变占空比电路根据其接收到的占空比指数值来调整时钟信号的占空比。 可变占空比电路将占空比调整的时钟信号提供给分频器电路。 该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。 然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

公开(公告)号：US20070103215A1

公开(公告)日：2007-05-10

申请号：US11269245

申请日：2005-11-08

申请人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K19/018521

摘要： A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

公开(公告)号：US20070071154A1

公开(公告)日：2007-03-29

申请号：US11236658

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/095

摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20070008003A1

公开(公告)日：2007-01-11

申请号：US11171758

申请日：2005-06-30

申请人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03K19/0175

CPC分类号： H03K19/018507

摘要： A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

摘要翻译： 一种用于在混合电压系统中位于不同功率边界的不同部件之间转换信号的方法和装置。 电平移位器系统包括连接到第一电压源的第一电平移位器电路。 第二电平移位器电路连接到第二电压源。 中间电平移位器电路具有连接到第一电平移位器电路的输出的输入。 中间电平移位器电路的输出连接到第二电平移位器电路的输入端。 中间电平移位器电路使用具有在第一电压源的第一电压和第二电压源的第二电压之间的中间的中间电压的中间电压源。

公开(公告)号：US20070005279A1

公开(公告)日：2007-01-04

申请号：US11168722

申请日：2005-06-28

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F19/00

CPC分类号： G01R31/318552

摘要： The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.

摘要翻译： 本发明提供了一种以降低的频率检查高频时钟屏蔽信号模式的方法。 选择第一移位寄存器的第一模式。 多个位以第一频率被加载在第一移位寄存器上。 选择第一移位寄存器的第二模式。 选择第二移位寄存器的第一模式。 多个比特被加载在第二移位寄存器上。 选择第二移位寄存器的第二模式。 选择第三移位寄存器的第一模式。 多个位被加载在第三移位寄存器上。 选择第三移位寄存器的第二模式，并且以第二频率从第三移位寄存器加载多个位，其中第二频率低于第一频率，从而提供用于检查高频时钟屏蔽信号模式 以减少的频率。

公开(公告)号：US20070001739A1

公开(公告)日：2007-01-04

申请号：US11171756

申请日：2005-06-30

申请人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/017581 ,  H03K19/00323 ,  H03K19/00346

摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.

摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

公开(公告)号：US20060117236A1

公开(公告)日：2006-06-01

申请号：US10988285

申请日：2004-11-12

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/263

摘要： A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

摘要翻译： 提供了一种方法，装置和计算机程序，用于产生错误检测状态和代码模式的校正。 通常，在低带宽实验室环境中进行dI / dt电路的全速测试是困难的。 然而，可以采用周期性地检测dI / dt电路的功能以指示成功或失败的电路。 当检测到错误时，电路允许用精确的代码替换错误的代码。 使用该电路，可以更容易地实现在低带宽实验室环境中进行dI / dt电路的全速测试。

公开(公告)号：US20060107242A1

公开(公告)日：2006-05-18

申请号：US10981157

申请日：2004-11-04

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： G01R31/2632

摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.

公开(公告)号：US07016798B2

公开(公告)日：2006-03-21

申请号：US10891759

申请日：2004-07-15

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： G06F11/00

CPC分类号： G01R31/2882

摘要： The present invention provides for determining gate speed parameters in a circuit. A first delay is selected. A second delay is selected, wherein the second delay is longer than the first delay. A clock signal is delayed as a function of the first delay. The clock signal is combined with the first delayed clock signal. A first pulse signal is produced from combining the clock signal with the first delayed clock signal. A clock signal is delayed as a function of the second delay. The clock signal is combined with the first delayed clock signal. A second pulse signal is produced from combining the clock signal with the second delayed clock signal. The first delayed clock signal is integrated. The second delayed clock signal is integrated. The first delayed integrated clock signal is compared with the second delayed integrated clock signal. When the first delayed integrated clock signal is greater than the second integrated clock signal, the gate delay is determined.

摘要翻译： 本发明提供了确定电路中的门速度参数。 选择第一个延迟。 选择第二延迟，其中第二延迟长于第一延迟。 时钟信号作为第一延迟的函数被延迟。 时钟信号与第一延迟时钟信号组合。 通过将时钟信号与第一延迟时钟信号组合来产生第一脉冲信号。 时钟信号作为第二延迟的函数被延迟。 时钟信号与第一延迟时钟信号组合。 通过将时钟信号与第二延迟时钟信号组合来产生第二脉冲信号。 第一个延迟时钟信号被集成。 第二个延迟时钟信号被集成。 将第一延迟积分时钟信号与第二延迟积分时钟信号进行比较。 当第一延迟积分时钟信号大于第二集成时钟信号时，确定门延迟。