公开(公告)号：US20110093750A1

公开(公告)日：2011-04-21

申请号：US12923276

申请日：2010-09-13

申请人： Michael John Williams ,  Stuart David Biles

发明人： Michael John Williams ,  Stuart David Biles

IPC分类号： G06F11/30 ,  G06F9/46 ,  G06F12/06 ,  G06F9/455 ,  G06F11/00 ,  G06F11/07

CPC分类号： G06F9/5077

摘要： A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.

摘要翻译： 处理器6具有诸如性能监视器12和上下文指针18之类的多个硬件资源。边界指示电路14,20存储可编程的边界值，其指示将硬件资源分成第一部分的边界位置， 第二部分。 资源控制电路16,22控制对硬件资源的访问，使得当程序执行电路8正在执行第一程序时，它响应于关于多少个所述多个硬件资源出现以返回第一值的查询，而当 程序执行电路正在执行第二程序，它通过返回与第二部分内的这些硬件资源相对应的值来响应于这样的查询。

公开(公告)号：US07877587B2

公开(公告)日：2011-01-25

申请号：US11449858

申请日：2006-06-09

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30101 ,  G06F9/3848

摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.

摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在先前的分支行为和存储在相应的分支历史寄存器20,22中的预测值之间使用不同的映射。这些不同的映射可以由放置在分支历史寄存器20,22的路径中的反相器或由加法器40,42 或以其他方式。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。

公开(公告)号：US07769955B2

公开(公告)日：2010-08-03

申请号：US11790811

申请日：2007-04-27

申请人： Emre Özer ,  Stuart David Biles

发明人： Emre Özer ,  Stuart David Biles

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3802 ,  G06F9/3851 ,  G06F12/0897

摘要： A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.

摘要翻译： 提供了一种数据处理装置，其中处理电路执行包括至少一个高优先级线程和至少一个较低优先级线程的多个程序线程。 从包含多个高速缓存级别的缓存存储器层次中检索线程所需的指令。 所述高速缓存存储器层级包括旁路路径，用于在执行所需指令的查找过程时省略所述高速缓存存储器层级的预定级别，以及当将所述所需指令返回给所述处理电路时绕过所述高速缓存存储器层级的所述预定级别。 当请求的指令用于较低优先级的线程时，默认使用旁路路径。

公开(公告)号：US20080282067A1

公开(公告)日：2008-11-13

申请号：US12078100

申请日：2008-03-27

申请人： Emre Ozer ,  Stuart David Biles

发明人： Emre Ozer ,  Stuart David Biles

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/4881

摘要： A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behaviour of the processor 2.

摘要翻译： 多线程顺序超标量处理器2包括发行阶段12，其包括发行电路22,24，用于根据当前选择的发行策略来选择要发布到执行单元14,16的指令。 多个不同的问题策略由相关联的不同策略电路28,30,32提供，并且策略电路28,30,32的这些实例中的哪一个被选择是由策略选择电路34根据检测到的动态行为 的处理器2。

公开(公告)号：US20080263341A1

公开(公告)日：2008-10-23

申请号：US11785918

申请日：2007-04-20

申请人： Emre Ozer ,  Alastair David Reid ,  Stuart David Biles

发明人： Emre Ozer ,  Alastair David Reid ,  Stuart David Biles

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0862 ,  G06F12/122

摘要： A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction data used by the processing circuitry. The prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Further update control circuitry is provided for modifying at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification to the at least one count value is dependent on the priority of the processing operation with which that update data is associated. As a result, the prediction data output for a received event associated with a high priority operation is more accurate than the prediction data output for a received event associated with a low priority operation.

摘要翻译： 提供了一种用于产生预测数据的数据处理装置和方法。 数据处理装置具有用于执行包括高优先级操作和低优先级操作的处理操作的处理电路，以及在执行这些处理操作期间发生的事件。 预测电路响应于所接收的事件以产生由处理电路使用的预测数据。 预测电路包括具有用于存储计数值的多个计数器条目的历史存储器和用于根据接收到的事件来识别至少一个计数器条目并用于使历史存储器输出存储在其中的计数值的索引电路 至少一个计数器条目，其中预测数据从输出计数值导出。 提供进一步的更新控制电路用于响应于由处理电路产生的更新数据来修改存储在历史存储器中的至少一个计数值。 更新控制电路具有优先级相关的修改机制，使得对至少一个计数值的修改取决于与该更新数据相关联的处理操作的优先级。 结果，与高优先级操作相关联的接收事件的预测数据输出比对于与低优先级操作相关联的接收事件的预测数据输出更精确。

公开(公告)号：US20080229052A1

公开(公告)日：2008-09-18

申请号：US11723189

申请日：2007-03-16

申请人： Emre Ozer ,  Stuart David Biles

发明人： Emre Ozer ,  Stuart David Biles

IPC分类号： G06F12/00

CPC分类号： G06F12/126

摘要： A data processing apparatus and method are provided for implementing a replacement scheme for entries of a storage unit. The data processing apparatus has processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread. A storage unit is then shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. A record is maintained identifying for each entry whether the information stored in that entry is associated with a high priority program thread or a lower priority program thread. Replacement circuitry is then responsive to a predetermined event in order to select a victim entry whose stored information is to be replaced. To achieve this, the replacement circuitry performs a candidate generation operation to identify a plurality of randomly selected candidate entries, and then references the record in order to preferentially select as the victim entry a candidate entry whose stored information is associated with a lower priority program thread. This improves the performance of the high priority program thread(s) by preferentially evicting from the storage unit entries associated with lower priority program threads.

摘要翻译： 提供了一种数据处理装置和方法，用于实现用于存储单元的条目的替换方案。 数据处理装置具有用于执行包括至少一个高优先级程序线程和至少一个较低优先级程序线程的多个程序线程的处理电路。 然后，存储单元在多个程序线程之间共享，并且具有用于存储用于在执行程序线程时由处理电路参考的信息的多个条目。 维护记录以识别每个条目，存储在该条目中的信息是否与高优先级程序线程或较低优先级的程序线程相关联。 然后，替换电路响应于预定事件，以便选择其存储的信息将被替换的受害者条目。 为了实现这一点，替换电路执行候选生成操作以识别多个随机选择的候选条目，然后引用该记录，以优先选择其存储的信息与较低优先级的程序线程相关联的候选条目作为受害者条目 。 这通过优先从与优先级较低的程序线程相关联的存储单元条目中逐出来来提高高优先级程序线程的性能。

公开(公告)号：US08621336B2

公开(公告)日：2013-12-31

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

公开(公告)号：US20130268930A1

公开(公告)日：2013-10-10

申请号：US13441400

申请日：2012-04-06

申请人： Ali SAIDI ,  Stuart David Biles ,  Simon John Craske

发明人： Ali SAIDI ,  Stuart David Biles ,  Simon John Craske

IPC分类号： G06F9/455

CPC分类号： G06F9/45558 ,  G06F12/0833 ,  G06F2009/45583

摘要： A data processing system 2 incorporates a plurality of processing elements 4, 6, 8, 10, 12 which may exchange broadcast maintenance messages, such as local instruction cache invalidation messages. Behaviour modification circuitry disposed either at the request generator, the request receiver or on route serves to modify the broadcast maintenance requests if one or more predetermined conditions are met. The predetermined conditions may include a message rate being exceeded, a message being redundant due to a preceding message, etc.

摘要翻译： 数据处理系统2包括可以交换诸如本地指令高速缓存无效消息的广播维护消息的多个处理元件4,6,8,10,12。 设置在请求发生器，请求接收器或路由上的行为修改电路用于在满足一个或多个预定条件时修改广播维护请求。 预定条件可以包括被超过的消息速率，消息由于前一消息而是冗余的等等

公开(公告)号：US08407025B2

公开(公告)日：2013-03-26

申请号：US12379617

申请日：2009-02-25

申请人： David Theodore Blaauw ,  Dennis Michael Sylvester ,  David Alan Fick ,  Stuart David Biles ,  Michael John Wieckowski ,  Scott McLean Hanson ,  Gregory Kengho Chen

发明人： David Theodore Blaauw ,  Dennis Michael Sylvester ,  David Alan Fick ,  Stuart David Biles ,  Michael John Wieckowski ,  Scott McLean Hanson ,  Gregory Kengho Chen

IPC分类号： G06F17/18 ,  G06F17/50 ,  G01R31/30

CPC分类号： G05B21/02 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

摘要翻译： 一种用于处理数据2的装置设置有时间 - 数字转换器18，其用于通过一个或多个通过处理级的信号路径来测量信号处理延迟。 该测量的延迟产生表示已经测量的信号处理延迟的多个实例的延迟值。 在软件控制下执行分析以基于已经产生的延迟值来估计通过处理阶段的最差情况信号处理延迟。 进行装置的工作参数（例如电源电压和时钟频率）的调整，以通过处理阶段提供足够的时间余量，以满足在没有过多余量的情况下估计的最差情况信号处理延迟。

公开(公告)号：US08332660B2

公开(公告)日：2012-12-11

申请号：US12003857

申请日：2008-01-02

申请人： Nigel Charles Paver ,  Stuart David Biles ,  Donald Felton

发明人： Nigel Charles Paver ,  Stuart David Biles ,  Donald Felton

IPC分类号： G06F11/30 ,  G06F12/14 ,  G06F7/04 ,  G06F17/30 ,  H04N7/16

CPC分类号： G06F21/74 ,  G06F12/1491 ,  G06F21/72

摘要： A data processor for processing data in a secure mode having access to secure data that is not accessible to the data processor when processing data in the non-secure mode. A further processing device for performing a task in response to a request from the data processor issued from the non-secure mode. The further processing device including a secure data store not accessible to processes running on the data processor when in the non-secure mode. Prior to issuing requests, the data processor in the secure mode performs a set up operation on the further data processing device storing secure data in the secure data store. In response to receipt of the request from the data processor operating in the non-secure mode, the further data processing device performs the task using data stored in the secure data store to access any secure data required.

摘要翻译： 一种用于以安全模式处理数据的数据处理器，其具有在处理非安全模式下的数据时能够访问数据处理器不可访问的安全数据。 一种用于响应于从非安全模式发出的来自数据处理器的请求来执行任务的另外的处理装置。 所述另外的处理设备包括当处于非安全模式时在数据处理器上运行的进程不可访问的安全数据存储器。 在发出请求之前，以安全模式执行的数据处理器对存储安全数据存储中的安全数据的另外的数据处理装置执行建立操作。 响应于以非安全模式操作的数据处理器的请求的接收，另外的数据处理设备使用存储在安全数据存储器中的数据来执行任务以访问所需的任何安全数据。