公开(公告)号：US20090303778A1

公开(公告)日：2009-12-10

申请号：US12511666

申请日：2009-07-29

申请人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G11C11/00

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

公开(公告)号：US07408829B2

公开(公告)日：2008-08-05

申请号：US11352699

申请日：2006-02-13

申请人： Jente B. Kuang ,  Hung Cai Ngo

发明人： Jente B. Kuang ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

摘要翻译： 本文提供了为集成电路配置电源管理系统的方法和布置。 功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。 集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。 这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。 这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

公开(公告)号：US20080130387A1

公开(公告)日：2008-06-05

申请号：US11741187

申请日：2007-04-27

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50012 ,  G11C2029/1204

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。

公开(公告)号：US06891399B2

公开(公告)日：2005-05-10

申请号：US10388977

申请日：2003-03-13

申请人： Hung Cai Ngo ,  Wendy Ann Belluomini ,  Robert Kevin Montoye

发明人： Hung Cai Ngo ,  Wendy Ann Belluomini ,  Robert Kevin Montoye

IPC分类号： G06F1/08 ,  H03K5/159 ,  H03K7/08 ,  H03K19/00 ,  G06F1/04 ,  H03H11/26 ,  H03K3/00

CPC分类号： G06F1/08 ,  H03K5/159 ,  H03K7/08

摘要： A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.

摘要翻译： 提供了一种用于从全局时钟信号产生至少两个时钟脉冲信号的时钟脉冲发生器。 时钟脉冲发生器包括用于接收具有上升沿和下降沿的时钟信号的至少一个输入端和用于可选地延迟与时钟信号的下降沿同步的脉冲信号的上升沿的机构。 时钟脉冲发生器还包括与时钟信号的上升沿同步的第一可选择持续时间脉冲和与可选择地延迟的上升沿同步的第二可选择持续时间脉冲。 时钟脉冲发生器还包括一个毛刺回避电路，用于消除时钟信号使用前的毛刺。

公开(公告)号：US06650145B2

公开(公告)日：2003-11-18

申请号：US10116612

申请日：2002-04-04

申请人： Hung Cai Ngo ,  Wendy Ann Belluomini ,  Robert Kevin Montoye

发明人： Hung Cai Ngo ,  Wendy Ann Belluomini ,  Robert Kevin Montoye

IPC分类号： H03K1900

CPC分类号： H03K19/0963

摘要： Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.

摘要翻译： 用于在动态逻辑器件的输出线上产生静态开关因子的电路和系统。 实现具有动态部分和静态部分的逻辑设备。 这样，只要设备执行的布尔运算的值不变，就保持输出逻辑状态。 此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。 非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积，并且避免了对保持器装置的需要。

公开(公告)号：US06292027B1

公开(公告)日：2001-09-18

申请号：US09440758

申请日：1999-11-16

申请人： Sand Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Osamu Takahashi

发明人： Sand Hoo Dhong ,  Hung Cai Ngo ,  Jaehong Park ,  Osamu Takahashi

IPC分类号： H03K19094

CPC分类号： H03K19/0013 ,  H03K19/0948

摘要： Fast low-power logic gates and method for evaluating logic signals reduce the effect of the power/speed tradeoff for parallel connected logic. A control circuit momentarily enables a high-current pullup or pulldown device after a connected input ladder switches from a conducting state to a non-conducting state. This allows a high current pullup or pulldown to be used for fast evaluation without increasing overall current drain, since the pullup action is momentary.

摘要翻译： 快速低功耗逻辑门和逻辑信号评估方法降低并联连接逻辑电源/速度权衡的影响。 在连接的输入梯形图从导通状态切换到非导通状态之后，控制电路暂时使能高电流上拉或下拉器件。 这允许高电流上拉或下拉用于快速评估，而不会增加总体电流消耗，因为上拉动作是瞬时的。

公开(公告)号：US06282557B1

公开(公告)日：2001-08-28

申请号：US09207483

申请日：1998-12-08

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F748

CPC分类号： G06F7/5443 ,  G06F7/5318

摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.

摘要翻译： 公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。 低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。 部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。 与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。 最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

公开(公告)号：US09274751B2

公开(公告)日：2016-03-01

申请号：US11776454

申请日：2007-07-11

申请人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

发明人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

IPC分类号： G06F7/533 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US09076509B2

公开(公告)日：2015-07-07

申请号：US12511666

申请日：2009-07-29

申请人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US08229992B2

公开(公告)日：2012-07-24

申请号：US11670357

申请日：2007-02-01

申请人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

发明人： Wendy Ann Belluomini ,  Hung Cai Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。