公开(公告)号：US08243866B2

公开(公告)日：2012-08-14

申请号：US12116329

申请日：2008-05-07

Applicant: Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

Inventor： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

IPC: H04L7/00 ,  H04L27/06

CPC classification number: H04L7/0062

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Abstract translation: 模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。 第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。 第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。 第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。 第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。 从第一和第二电位定时误差信号导出期望的定时误差信号。 所需的定时误差信号用于确定信号采样是早还是晚。

公开(公告)号：US08229020B2

公开(公告)日：2012-07-24

申请号：US12409236

申请日：2009-03-23

Applicant: Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

Inventor： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

IPC: H04B15/00 ,  H04B1/10 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H04L7/0337 ,  H04L2025/03503

Abstract: A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.

Abstract translation: 公开了一种数据通信系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。 接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。 为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。 为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

公开(公告)号：US08218702B2

公开(公告)日：2012-07-10

申请号：US12388223

申请日：2009-02-18

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC: H04L7/00

CPC classification number: H04L7/0062

Abstract: A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.

Abstract translation: 公开了一种从输入数据信号中恢复数据的系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。 为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。 该相位基于从数据信号恢复的时钟。 响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

公开(公告)号：US08155214B2

公开(公告)日：2012-04-10

申请号：US12612449

申请日：2009-11-04

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC: H04B3/00 ,  H04L25/00

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

Abstract translation: 公开了一种不对称DFE接收器电路。 接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。 比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。 所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。 调整速率可以根据接收到的信号是转换位还是非转换位而变化。

公开(公告)号：US20090238318A1

公开(公告)日：2009-09-24

申请号：US12053121

申请日：2008-03-21

Applicant: Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

Inventor： Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

IPC: H04L7/00

CPC classification number: H04L25/068

Abstract: A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

Abstract translation: 提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。 在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。 接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。 通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

公开(公告)号：US07437491B2

公开(公告)日：2008-10-14

申请号：US11265885

申请日：2005-11-02

Applicant: Gabriel C. Risk ,  Dawei Huang ,  Jason H. Bau

Inventor： Gabriel C. Risk ,  Dawei Huang ,  Jason H. Bau

IPC: G06F3/00 ,  H04N7/00

CPC classification number: H04L7/0083 ,  H04L7/046 ,  H04L7/10 ,  H04L2007/045

Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.

Abstract translation: 改进的时钟和数据恢复涉及在发送同步帧之前发送一个或多个空帧。 接收组件检测同步帧锁定到由发射组件在信号路径上发送的数据信号。 在同步帧之前发送的一个或多个空帧在接收到同步帧之前导致信号路径的建立，从而减少或消除先前在同步帧上发送的数据的影响。

公开(公告)号：US20060167941A1

公开(公告)日：2006-07-27

申请号：US11087807

申请日：2005-03-24

Applicant: Dawei Huang ,  Ling Qian

Inventor： Dawei Huang ,  Ling Qian

IPC: G06F17/00

CPC classification number: G06Q30/02 ,  H04M3/5141 ,  H04M3/5191

Abstract: The method manages, for example, a database to track customer service sessions over a plurality of communication media used by a customer.

Abstract translation: 该方法例如管理数据库以跟踪客户使用的多个通信媒体上的客户服务会话。

公开(公告)号：USD1061723S1

公开(公告)日：2025-02-11

申请号：US29959516

申请日：2024-08-26

Applicant: Dawei Huang

Designer： Dawei Huang

公开(公告)号：US08181058B2

公开(公告)日：2012-05-15

申请号：US12683147

申请日：2010-01-06

Applicant: Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

Inventor： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

IPC: G06F1/04 ,  G06F13/42 ,  G06F12/00 ,  G06F11/00 ,  H03L7/00 ,  H03K5/01 ,  H03K3/017 ,  H03K7/04 ,  H03K9/00 ,  H04L12/28 ,  H04J3/06 ,  H03H7/30 ,  H04B15/00 ,  G01R13/00 ,  G01R25/00 ,  G06K5/04 ,  H03M13/00

CPC classification number: H04L7/0054 ,  H04L7/0062 ,  H04L7/0334

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract translation: 描述接收机电路。 在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样 基于第二时钟信号。 另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。 基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联 接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

公开(公告)号：US20110252542A1

公开(公告)日：2011-10-20

申请号：US13141076

申请日：2010-07-07

Applicant: Dawei Huang

Inventor： Dawei Huang

IPC: A41D27/06

CPC classification number: A41B3/06

Abstract: The present invention relates to a decorative collar stay comprising a main body of collar stay; a mounting member is arranged on said main body of collar stay, and a decorative member is arranged on said mounting member. By disposing a decorative member and a mounting member on the main body of a collar stay, when the decorative collar stay is used, the main body of the collar stay can not only be inserted into the collar for support, but also can bring beautiful effect by putting out the decorative member from the collar to locate at the neckline. Further, the decorative member is connected to the main body of the collar stay through mounting member, so the brace for the collar will be enhanced.

Abstract translation: 本发明涉及一种装饰领座，包括一个领座主体; 安装构件布置在所述套环的主体上，并且装饰构件布置在所述安装构件上。 通过将装饰构件和安装构件设置在衣领的主体上，当使用装饰衣领时，衣领的主体不仅可以插入到用于支撑的衣领中，而且可以带来美丽的效果 通过从衣领放出装饰构件来定位在领口。 此外，装饰构件连接到套环的主体保持穿过安装构件，因此用于衣领的支架将被增强。