公开(公告)号：US06631255B1

公开(公告)日：2003-10-07

申请号：US09605481

申请日：2000-06-28

申请人： Shimen K. Claxton ,  Bert K. Oyama ,  Barry R. Allen ,  Mark Kintis ,  Andrew D. Smith ,  Craig R. Talbott ,  David J. Brunone ,  Donald R. Martin ,  William M. Skones ,  Vincent C. Moretti

发明人： Shimen K. Claxton ,  Bert K. Oyama ,  Barry R. Allen ,  Mark Kintis ,  Andrew D. Smith ,  Craig R. Talbott ,  David J. Brunone ,  Donald R. Martin ,  William M. Skones ,  Vincent C. Moretti

IPC分类号： H04B118

CPC分类号： H04B1/0007 ,  H03D7/163 ,  H04B1/0003 ,  H04B1/0028 ,  H04B1/0032 ,  H04B1/28

摘要： A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC (20) employs delta-sigma processing to provide digital conversion over the complete frequency band. In an alternate embodiment, the frequency down-conversion is performed in a double down-conversion process so that a less complex ADC (62) can be used.

摘要翻译： 一种用于无线电信系统的接收机（10），其提供接收信号的相对宽带信号处理，而不增加信号失真，使得可以同时处理多个接收信号。 接收器（10）包括专用LNA（16），降频转换器（18）和ADC（20），以在维持接收机性能的同时执行宽带信号处理。 降频转换器（18）采用合适的混频器（28），BPA（32），衰减器（34）和变压器（36），其被调谐以在期望的宽带上提供期望的频率下变频和幅度控制。 根据ADC的特定性能标准（20）选择下转换器器件。 在接收器（10）中包括一个专门的数字信道化器（22），其接收来自ADC（20）的数字信号，并将信号分离成多个信道。 在一个实施例中，在单个下变频处理中执行降频转换，并且ADC（20）采用delta-sigma处理来在整个频带上提供数字转换。 在替代实施例中，在双下变频过程中执行降频转换，使得可以使用较不复杂的ADC（62）。

公开(公告)号：US06396338B1

公开(公告)日：2002-05-28

申请号：US09427453

申请日：1999-10-26

申请人： Marshall Y. Huang ,  Mark Kintis ,  Robert E. Kasody

发明人： Marshall Y. Huang ,  Mark Kintis ,  Robert E. Kasody

IPC分类号： H03D300

CPC分类号： H03D3/06

摘要： A variable delay line detector (34, 48, 66)includes a power splitter (36, 50, 68), a mixer (44, 62, 72) and a variable delay line (42,52, 70). Various devices are suitable for the variable delay line (42, 52, 70), such as a non-linear transmission line (NLTL). By providing a variable delay line, the variable delay line detector (34, 48, 66) is adapted to be programmed in real time thus making it suitable in applications where the phase and or frequency of the input signal varies. As such, the variable delay line detector (34, 48, 66) may be used in applications heretofore unknown, such &a an inexpensive demodulator in a frequency hopped spread spectrum system.

摘要翻译： 可变延迟线检测器（34,48,66）包括功率分配器（36,50,68），混合器（44,62,72）和可变延迟线（42,52,70）。 各种装置适用于诸如非线性传输线（NLTL）的可变延迟线（42,52,70）。 通过提供可变延迟线，可变延迟线检测器（34,48,66）适于实时编程，从而使其适用于输入信号的相位和/或频率变化的应用。 因此，可变延迟线检测器（34,48,66）可以用于迄今为止未知的应用中，例如在频率跳频扩频系统中是便宜的解调器。

公开(公告)号：US6064325A

公开(公告)日：2000-05-16

申请号：US133037

申请日：1998-08-11

申请人： Richard A. Fields ,  David L. Rollins ,  Stephen R. Perkins ,  Eric L. Upton ,  Elizabeth T. Kunkee ,  Lawrence J. Lembo ,  Juan C. Carillo, Jr. ,  Mark Kintis

发明人： Richard A. Fields ,  David L. Rollins ,  Stephen R. Perkins ,  Eric L. Upton ,  Elizabeth T. Kunkee ,  Lawrence J. Lembo ,  Juan C. Carillo, Jr. ,  Mark Kintis

IPC分类号： G02F7/00 ,  H03M1/00

CPC分类号： G02F7/00

摘要： A frequency modulation-based optical analog-to-digital converter utilizes a downward-folding, successive approximation approach. A series of stages is utilized to generate bits in the digital signal. In each stage, complementary low and high bandpass filters collectively cover a bandpass frequency range from a low frequency to a high frequency. The high frequency filtered signal from the high bandpass filter is observed to obtain a bit in the digital word. By performing the folding operations in the frequency domain, the converter avoids the difficult task of optical power subtraction, relying instead on frequency down-conversions. The high frequency filtered signal passed by the high bandpass filter is then downconverted and added to the low pass filter signal to generate a modulated signal for the next stage.

摘要翻译： 基于频率调制的光学模数转换器利用向下折叠的逐次近似方法。 利用一系列级来产生数字信号中的位。 在每个阶段，互补的低和高带通滤波器共同覆盖从低频到高频的带通频率范围。 观察到来自高带通滤波器的高频滤波信号以获得数字字中的位。 通过在频域执行折叠操作，转换器避免了光功率减法的困难任务，而是依靠降频转换。 然后，由高带通滤波器通过的高频滤波信号被下变频并加到低通滤波器信号中，以生成下一级的调制信号。

公开(公告)号：US6049250A

公开(公告)日：2000-04-11

申请号：US54934

申请日：1998-04-03

申请人： Mark Kintis ,  Petar Tomasevic

发明人： Mark Kintis ,  Petar Tomasevic

IPC分类号： H03F3/60

CPC分类号： H03F3/607

摘要： A distributed amplifier topology with distributed feedback includes a plurality of amplifier stages, each of which includes a FET, MESFET or HEMT. A negative feedback network is provided with each amplifier stage which enables the gain of the distributed amplifier to be reduced by varying the negative feedback. An important aspect of the invention relates to the fact that the gain can be varied with virtually no affect on the bandwidth performance of the product and without significantly affecting the return loss, IP3 and noise figure performance of the device.

摘要翻译： 具有分布式反馈的分布式放大器拓扑包括多个放大器级，每个放大器级包括FET，MESFET或HEMT。 每个放大器级都提供负反馈网络，通过改变负反馈能够降低分布式放大器的增益。 本发明的一个重要方面涉及增益可以改变，实际上对产品的带宽性能没有影响，并且不显着影响设备的回波损耗，IP3和噪声系数性能。

公开(公告)号：US08610515B2

公开(公告)日：2013-12-17

申请号：US13103634

申请日：2011-05-09

申请人： Xing Lan ,  Mark Kintis ,  Chad Hansen

发明人： Xing Lan ,  Mark Kintis ,  Chad Hansen

IPC分类号： H01P1/18

CPC分类号： H01P9/02

摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.

摘要翻译： 一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。 在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。 通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。 在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。 平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。 在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

公开(公告)号：US20120286899A1

公开(公告)日：2012-11-15

申请号：US13103634

申请日：2011-05-09

申请人： Xing Lan ,  Mark Kintis ,  Chad Hansen

发明人： Xing Lan ,  Mark Kintis ,  Chad Hansen

IPC分类号： H01P1/18

CPC分类号： H01P9/02

摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.

摘要翻译： 一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。 在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。 通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。 在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。 平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。 在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

公开(公告)号：US07476606B2

公开(公告)日：2009-01-13

申请号：US11390772

申请日：2006-03-28

申请人： Dean Tran ,  Alan Hirschberg ,  Ha K. DeMarco ,  Luis Rochin ,  Thomas Chung ,  Mark Kintis ,  Steven J. Mass

发明人： Dean Tran ,  Alan Hirschberg ,  Ha K. DeMarco ,  Luis Rochin ,  Thomas Chung ,  Mark Kintis ,  Steven J. Mass

IPC分类号： H01L21/00 ,  H01L21/28

CPC分类号： H01L21/2007

摘要： Ultra-high speed semiconductors that are usually very thin and therefore very fragile still require connection to a circuit board and a heat transfer pathway. Ultra-high speed circuits and semiconductor devices are provided with a carrier plate formed on the backside of a wafer or substrate by a variety of deposition methods. The carrier plate is a series of metal layers, each being selected to enable the attachment of a relatively thick copper carrier plate to the backside of the substrate or wafer.

摘要翻译： 通常非常薄且因此非常脆弱的超高速半导体仍需要连接到电路板和传热通路。 超高速电路和半导体器件具有通过各种沉积方法形成在晶片或衬底的背面上的载体板。 载体板是一系列金属层，每个金属层被选择为能够将相对厚的铜载体板附接到基板或晶片的背面。

公开(公告)号：US07348866B2

公开(公告)日：2008-03-25

申请号：US11268413

申请日：2005-11-02

申请人： Ming-Jong Shiau ,  Phu H. Tran ,  Alex T. Chau ,  Mark Kintis ,  George W. Schreyer

发明人： Ming-Jong Shiau ,  Phu H. Tran ,  Alex T. Chau ,  Mark Kintis ,  George W. Schreyer

IPC分类号： H03H7/01

CPC分类号： H03H7/0115 ,  H03H7/1775 ,  H03H2001/0078

摘要： An LC filter structure and method for its fabrication, in which multiple shunt capacitors, multiple shunt inductors and multiple coupling inductors are printed on a metal layer formed on a thin dielectric substrate. The capacitors have first electrodes that are formed as spatially separated regions of the metal layer, and a common second electrode formed by a ground plane on the substrate. The shunt inductors are formed as spiral traces connected to the separated regions and to the ground plane, through conductive vias. The coupling inductors are similarly formed as spiral traces in the gaps between the separated regions, the ends of each coupling inductor being connected to respective adjacent regions of the metal layer.

摘要翻译： 一种用于其制造的LC滤波器结构及其制造方法，其中多个分流电容器，多个分流电感器和多个耦合电感器被印刷在形成在薄介电基片上的金属层上。 电容器具有形成为金属层的空间分离区域的第一电极和由基板上的接地平面形成的公共第二电极。 分流电感器通过导电通孔形成为连接到分离区域和接地平面的螺旋迹线。 耦合电感器类似地形成为分离区域之间的间隙中的螺旋迹线，每个耦合电感器的端部连接到金属层的各个相邻区域。

公开(公告)号：US20070235744A1

公开(公告)日：2007-10-11

申请号：US11390772

申请日：2006-03-28

申请人： Dean Tran ,  Alan Hirschberg ,  Ha DeMarco ,  Luis Rochin ,  Thomas Chung ,  Mark Kintis ,  Steven Mass

发明人： Dean Tran ,  Alan Hirschberg ,  Ha DeMarco ,  Luis Rochin ,  Thomas Chung ,  Mark Kintis ,  Steven Mass

IPC分类号： H01L33/00

CPC分类号： H01L21/2007

摘要： Ultra-high speed semiconductors that are usually very thin and therefore very fragile still require connection to a circuit board and a heat transfer pathway. Ultra-high speed circuits and semiconductor devices are provided with a carrier plate formed on the backside of a wafer or substrate by a variety of deposition methods. The carrier plate is a series of metal layers, each being selected to enable the attachment of a relatively thick copper carrier plate to the backside of the substrate or wafer.

摘要翻译： 通常非常薄且因此非常脆弱的超高速半导体仍需要连接到电路板和传热通路。 超高速电路和半导体器件具有通过各种沉积方法形成在晶片或衬底的背面上的载体板。 载体板是一系列金属层，每个金属层被选择为能够将相对厚的铜载体板附接到基板或晶片的背面。

公开(公告)号：US06801583B1

公开(公告)日：2004-10-05

申请号：US09605114

申请日：2000-06-28

申请人： Shimen K. Claxton ,  Bert K. Oyama ,  Mark Kintis ,  Andrew D. Smith ,  Craig R. Talbott ,  Donald R. Martin ,  William M. Skones ,  Ronald P. Smith ,  Vincent C. Moretti

发明人： Shimen K. Claxton ,  Bert K. Oyama ,  Mark Kintis ,  Andrew D. Smith ,  Craig R. Talbott ,  Donald R. Martin ,  William M. Skones ,  Ronald P. Smith ,  Vincent C. Moretti

IPC分类号： H03K900

CPC分类号： H04B1/0007 ,  H04B1/0003 ,  H04B1/28

摘要： A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC (20) employs delta-sigma processing to provide digital conversion over the complete frequency band.

摘要翻译： 一种用于无线电信系统的接收机（10），其提供接收信号的相对宽带信号处理，而不增加信号失真，使得可以同时处理多个接收信号。 接收器（10）包括专用LNA（16），降频转换器（18）和ADC（20），以在维持接收机性能的同时执行宽带信号处理。 在接收器（10）中包括一个专门的数字信道化器（22），其接收来自ADC（20）的数字信号，并将信号分离成多个信道。 在一个实施例中，在单个下变频处理中执行降频转换，并且ADC（20）采用delta-sigma处理来在整个频带上提供数字转换。