公开(公告)号：US09412695B1

公开(公告)日：2016-08-09

申请号：US14641699

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hiroaki Niimi ,  Andreas Knorr

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L29/7851 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/66795

Abstract: Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.

Abstract translation: 提供了用于电路结构晶体管的方法和互连结构。 所述方法包括例如：在衬底上提供一个或多个鳍片，以及在鳍片和衬底上方的绝缘材料; 提供延伸到所述绝缘材料中的阻挡结构，所述阻挡结构沿着所述鳍片的相对侧布置; 暴露所述鳍片和所述屏障结构的一部分; 以及形成在所述翅片上延伸的互连结构，所述阻挡结构将所述互连结构限制在横向于所述鳍片的限定尺寸。 暴露鳍状物和阻挡结构的部分可以包括用蚀刻剂均匀地蚀刻绝缘材料，该蚀刻剂选择性地蚀刻绝缘材料而不影响阻挡结构的阻挡材料。

公开(公告)号：US09245885B1

公开(公告)日：2016-01-26

申请号：US14674656

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second recessed gate structures, recessing the second recessed gate structure so as to define a further recessed second gate structure that exposes a channel structure within a gate cavity, forming first and second gate cap layers in first and second replacement gate cavities, respectively, forming a recess in the second gate cap layer that exposes the channel structure, forming a semiconductor material on the exposed portion of the channel structure within the recess in the second gate cap layer so as to define a first source/drain region for the vertical FinFET device, and forming various contact structures to the gates of the devices and the first source/drain region.

Abstract translation: 本文公开的一种说明性方法包括形成第一和第二凹陷栅极结构，凹陷第二凹陷栅极结构以便限定暴露栅极腔内的沟道结构的另外凹陷的第二栅极结构，形成第一和第二栅极 分别在第一和第二替换栅极腔中形成盖层，在第二栅极盖层中形成露出沟道结构的凹槽，在第二栅极盖层的凹槽内的沟道结构的暴露部分上形成半导体材料，以便 以限定用于垂直FinFET器件的第一源极/漏极区域，以及向器件和第一源极/漏极区域的栅极形成各种接触结构。

公开(公告)号：US20150333136A1

公开(公告)日：2015-11-19

申请号：US14812150

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US09147730B2

公开(公告)日：2015-09-29

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150249127A1

公开(公告)日：2015-09-03

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US09048171B2

公开(公告)日：2015-06-02

申请号：US14220475

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven R. Soss ,  Andreas Knorr

IPC: H01L21/00 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

Abstract translation: 形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。 一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道 导线来控制电阻半导体元件的电阻值。 该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。