公开(公告)号：US09190260B1

公开(公告)日：2015-11-17

申请号：US14540504

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L21/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150249036A1

公开(公告)日：2015-09-03

申请号：US14195484

申请日：2014-03-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract translation: 本文公开的一个示例涉及将源极/漏极导电触点形成到第一和第二源极/漏极区域，第一源极/漏极区域位于具有第一栅极间距尺​​寸的第一对晶体管器件之间，第二源极/漏极区域被定位 在具有大于第一栅极间距尺​​寸的第二栅极间距尺​​寸的第二对晶体管器件之间，其中第一和第二对晶体管器件具有栅极结构和邻近栅极结构定位的侧壁间隔物。

公开(公告)号：US09082852B1

公开(公告)日：2015-07-14

申请号：US14560472

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-Chen Yeh

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Abstract translation: FinFET包括支撑第一晶体管和第二晶体管的半导体鳍片。 第一晶体管栅极电极延伸在鳍片的第一沟道区域上，第二晶体管栅电极在鳍片的第二沟道区域上延伸。 翅片顶部的外延生长材料在第一晶体管栅电极的第一侧上形成升高的源极区，在第一晶体管栅电极的第二侧和第二晶体管栅电极的第一侧之间的中间区域，以及 在所述第二晶体管栅电极的第二侧上的升高的漏极区。 第一和第二晶体管栅极彼此短路，其中第一晶体管被配置为具有第一阈值电压，并且第二晶体管被配置为具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09000537B2

公开(公告)日：2015-04-07

申请号：US14333683

申请日：2014-07-17

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

公开(公告)号：US08987094B2

公开(公告)日：2015-03-24

申请号：US13937939

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract translation: 翅片场效应晶体管集成电路（FinFET IC）具有从半导体衬底延伸的多个鳍，其中在相邻鳍之间限定有槽。 第二电介质位于槽内，并且翅片的突出部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US20150061040A1

公开(公告)日：2015-03-05

申请号：US14538401

申请日：2014-11-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US08962413B1

公开(公告)日：2015-02-24

申请号：US14524076

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  William J. Taylor, Jr.

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract translation: 这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。 在一个示例中，该方法包括在限定鳍片的半导体衬底中形成多个间隔开的沟槽，在沟槽中形成覆盖翅片下部的第一绝缘材料层，但暴露鳍片的上部 并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。 所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层， 以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

公开(公告)号：US20150041869A1

公开(公告)日：2015-02-12

申请号：US14526126

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/423 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US08906754B2

公开(公告)日：2014-12-09

申请号：US13839802

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US20140346599A1

公开(公告)日：2014-11-27

申请号：US13902369

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7851

Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个鳍结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。