公开(公告)号：US09666791B2

公开(公告)日：2017-05-30

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/08 ,  H01L21/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20160190207A1

公开(公告)日：2016-06-30

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

Abstract translation: 提供了包括用于磁阻随机存取存储器（MRAM）的磁性隧道结（MTJ）和用于制造这种集成电路的方法的集成电路。 在一个示例中，制造集成电路的方法包括在金属互连上形成下电极。 金属互连设置在半导体衬底之上并且与基本上垂直于半导体衬底的法线对准。 下电极包括导电金属插头。 在与正常轴对准的下电极上形成MTJ堆叠。

公开(公告)号：US20160379881A1

公开(公告)日：2016-12-29

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。

公开(公告)号：US09190260B1

公开(公告)日：2015-11-17

申请号：US14540504

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L21/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150087149A1

公开(公告)日：2015-03-26

申请号：US14037774

申请日：2013-09-26

Applicant: Globalfoundries, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。

公开(公告)号：US09576852B2

公开(公告)日：2017-02-21

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。

公开(公告)号：US09165770B2

公开(公告)日：2015-10-20

申请号：US14037774

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。

公开(公告)号：US10283505B2

公开(公告)日：2019-05-07

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/52 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L23/528 ,  H01L21/02 ,  H01L21/321 ,  H01L27/02 ,  H01L29/49

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US09691971B2

公开(公告)日：2017-06-27

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.