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    SILICON-ON-INSULATOR CHIP STRUCTURE WITH SUBSTRATE-EMBEDDED OPTICAL WAVEGUIDE AND METHOD
    31.
    发明申请
    SILICON-ON-INSULATOR CHIP STRUCTURE WITH SUBSTRATE-EMBEDDED OPTICAL WAVEGUIDE AND METHOD 有权

    公开(公告)号：US20220196909A1

    公开(公告)日：2022-06-23

    申请号：US17131997

    申请日：2020-12-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Judson R. Holt ,  Yusheng Bian ,  Dali Shao

    IPC: G02B6/122 ,  G02B6/12 ,  H01L29/06

    Abstract: Disclosed is a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide. Also disclosed is a method for forming the SOI chip structure. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process that results in the SOI structure. Subsequently, front-end-of-the-line (FEOL) processing can be performed to form additional optical devices and/or electronic devices in and/or above the silicon layer. By embedding an optical waveguide within the substrate prior to wafer bonding as opposed to forming it during FEOL processing, strict limitations on the dimensions of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large such that the cut-off wavelength can be relatively long. Thus, such a substrate-embedded optical waveguide brings different functionality to the SOI chip structure as compared to FEOL optical waveguides.

    Source/drain regions for transistor devices and methods of forming same
    35.
    发明授权
    Source/drain regions for transistor devices and methods of forming same 有权

    公开(公告)号：US11094822B1

    公开(公告)日：2021-08-17

    申请号：US16751380

    申请日：2020-01-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

    IPC: H01L29/76 ,  H01L21/84 ,  H01L29/80 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

    STRUCTURE AND METHOD FOR RANDOM CODE GENERATION
    36.
    发明申请
    STRUCTURE AND METHOD FOR RANDOM CODE GENERATION 有权

    公开(公告)号：US20210141610A1

    公开(公告)日：2021-05-13

    申请号：US16677717

    申请日：2019-11-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

    IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

    Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

    LIMITING LATERAL EPITAXY GROWTH AT N-P BOUNDARY USING INNER SPACER, AND RELATED STRUCTURE
    37.
    发明申请
    LIMITING LATERAL EPITAXY GROWTH AT N-P BOUNDARY USING INNER SPACER, AND RELATED STRUCTURE 有权

    公开(公告)号：US20210125984A1

    公开(公告)日：2021-04-29

    申请号：US16660868

    申请日：2019-10-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Judson R. Holt ,  Jiehui Shu

    IPC: H01L27/092 ,  H01L21/8238

    Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

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