公开(公告)号：US20210399126A1

公开(公告)日：2021-12-23

申请号：US16906490

申请日：2020-06-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Judson R. Holt ,  Haiting Wang ,  Yanping Shen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

Abstract: An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material.

公开(公告)号：US11145725B2

公开(公告)日：2021-10-12

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Qizhi Liu ,  Vibhor Jain ,  Judson R. Holt ,  Herbert Ho ,  Claude Ortolland ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US11094822B1

公开(公告)日：2021-08-17

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/76 ,  H01L21/84 ,  H01L29/80 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US20210141610A1

公开(公告)日：2021-05-13

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US20210125984A1

公开(公告)日：2021-04-29

申请号：US16660868

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Jiehui Shu

IPC: H01L27/092 ,  H01L21/8238

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

公开(公告)号：US20240282852A1

公开(公告)日：2024-08-22

申请号：US18171765

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Kaustubh Shanbhag ,  Rajendran Krishnasamy ,  Judson R. Holt

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/0642 ,  H01L29/66681

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：US11942534B2

公开(公告)日：2024-03-26

申请号：US17745178

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L23/373 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L23/3738 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.

公开(公告)号：US11916109B2

公开(公告)日：2024-02-27

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

公开(公告)号：US11881523B2

公开(公告)日：2024-01-23

申请号：US17740725

申请日：2022-05-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/1004 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.

公开(公告)号：US11881395B2

公开(公告)日：2024-01-23

申请号：US17644939

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. Holt ,  Hong Yu ,  Alexander M. Derrickson

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor on a semiconductor fin and methods to form the same. A bipolar transistor structure according to the disclosure may include a doped semiconductor layer coupled to a base contact. A first semiconductor fin on the doped semiconductor layer may have a first doping type. An emitter/collector (E/C) material may be on a sidewall of an upper portion of the first semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.