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公开(公告)号：US20200167530A1
公开(公告)日：2020-05-28
申请号：US16072279
申请日：2016-02-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.
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公开(公告)号：US10261487B1
公开(公告)日：2019-04-16
申请号：US15885193
申请日：2018-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , John Paul Strachan , Le Zheng
IPC: G05B19/045 , G11C15/04
Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.
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公开(公告)号：US10180820B2
公开(公告)日：2019-01-15
申请号：US15282021
申请日：2016-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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公开(公告)号：US10109346B2
公开(公告)日：2018-10-23
申请号：US15320788
申请日：2014-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Hans S. Cho , Gary Gibson , Brent Buchanan
Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.
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公开(公告)号：US10079059B2
公开(公告)日：2018-09-18
申请号：US15324687
申请日：2014-07-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
CPC classification number: G11C13/004 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2213/75
Abstract: Memristor cell read margin enhancement employs programming switched memristor sub-bits of a memristor cell with a first resistive state to increase a relative read margin of the memristor cell. The switched memristor sub-bits of the memristor cell are connected in series. The read margin of the memristor cell is increased relative to a read margin of either of the switched memristor sub-bits.
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Patent Agency Ranking
公开(公告)号：US09953728B2
公开(公告)日：2018-04-24
申请号：US15216589
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J Merced Grafals , Brent Buchanan , Le Zheng
CPC classification number: G11C29/789 , G11C13/0021 , H01L45/04 , H01L45/16
Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
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公开(公告)号：US20180040374A1
公开(公告)日：2018-02-08
申请号：US15228559
申请日：2016-08-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Le Zheng , Brent Buchanan , John Paul Strachan
IPC: G11C15/04
CPC classification number: G11C15/046
Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.
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公开(公告)号：US20170221579A1
公开(公告)日：2017-08-03
申请号：US15500568
申请日：2015-04-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
CPC classification number: G11C27/02 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C27/00 , H03H15/00
Abstract: According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.
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公开(公告)号：US20170221562A1
公开(公告)日：2017-08-03
申请号：US15500472
申请日：2015-04-15
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0064 , G11C13/0097 , G11C2013/0066 , G11C2013/0073 , G11C2013/0078 , G11C2213/77
Abstract: One example includes a resistive random access memory (RRAM) system. The system includes a resistive memory element to store a binary state based on a resistance of the resistive memory element. The system also includes an RRAM write circuit to generate a current through the resistive memory element to provide a write voltage across the resistive memory element to set the resistance of the resistive memory element. The system further includes a write shutoff circuit to monitor a change in the write voltage as a function of time to deactivate the RRAM write circuit in response to a change in the binary state of the resistive memory element.
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公开(公告)号：US09721661B1
公开(公告)日：2017-08-01
申请号：US15216011
申请日：2016-07-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G11C15/04
CPC classification number: G11C15/046 , G11C13/0002 , G11C13/0007 , G11C15/04
Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.
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