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公开(公告)号：US20240389461A1
公开(公告)日：2024-11-21
申请号：US18661690
申请日：2024-05-12
Inventor： Xingsheng Wang , Zichong Zhang , Xiangshui MIAO
IPC: H10N30/045 , H01L29/51
Abstract: The disclosure discloses a thermal reawakening operation method and system for enhancing polarization of a hafnium-based ferroelectric film, belonging to the field of micro-nanoelectronic technology, which includes the following. S1. Heating is performed on the hafnium-based ferroelectric thin film. S2. A pulse voltage having multiple cycles is applied to the hafnium-based ferroelectric thin film. S3.The hafnium-based ferroelectric thin film is cooled to an initial temperature. In the disclosure, through the thermal reawakening operation, a certain amount of oxygen vacancies are generated, and the non-polarized phase is transformed into the polarized phase, the polarization value of the hafnium-based ferroelectric film can be significantly improved at a low cost and with a simple operation, thereby the performance of the hafnium-based ferroelectric device is significantly improved.
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公开(公告)号：US20240379159A1
公开(公告)日：2024-11-14
申请号：US18033075
申请日：2022-01-25
Inventor： Hao TONG , Binhao Wang , Xiangshui MIAO
IPC: G11C13/00
Abstract: Disclosed are an OTS-based dynamic storage structure and an operation method thereof. The OTS-based dynamic storage structure includes a plurality of storage units distributed in an array, and each storage unit includes an OTS gating transistor and a storage capacitor. The OTS gating transistor has two states, namely, high resistance state and low resistance state. When the voltage across the OTS gating transistor exceeds the threshold voltage Vth, the OTS gating transistor is switched from the high resistance state to the low resistance state. When the voltage across the OTS gating transistor in the low resistance state is lower than the holding voltage Vhold, the OTS gating transistor is switched from the low resistance state to the high resistance state.
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公开(公告)号：US20240265962A1
公开(公告)日：2024-08-08
申请号：US18021177
申请日：2022-08-12
Inventor： Hao TONG , Binhao WANG , Xiangshui MIAO
IPC: G11C11/4096 , G11C11/406 , G11C11/4093
CPC classification number: G11C11/4096 , G11C11/40603 , G11C11/4093 , G11C2211/4068
Abstract: A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.
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公开(公告)号：US20230099931A1
公开(公告)日：2023-03-30
申请号：US17642706
申请日：2021-01-05
Inventor： Xiaomin CHENG , Han LI , Yuntao ZENG , Yunlai ZHU , Xiangjun LIU , Xiangshui MIAO
IPC: H01L47/00
Abstract: A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.
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公开(公告)号：US20220344584A1
公开(公告)日：2022-10-27
申请号：US17762742
申请日：2020-10-21
Inventor： Xiaomin CHENG , Jinlong FENG , Ming XU , Meng XU , Xiangshui MIAO
Abstract: A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film includes first phase-change layers (7) and second phase-change layers (8) that are alternately stacked to form a periodic structure; during crystallization, the first phase-change layer (7) has a conventional positive density change, and the second phase-change layer (8) has an abnormal negative density change, therefore, the abnormal density reduction and volume increase of the second phase-change layer (8) during crystallization can be used to offset the volume reduction of the first phase-change layer (7) during crystallization.
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Patent Agency Ranking
公开(公告)号：US20220271089A1
公开(公告)日：2022-08-25
申请号：US17043672
申请日：2019-09-23
Inventor： Hao TONG , Wang CAI , Xiangshui MIAO
Abstract: The disclosure belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method includes: preparing a multilayer structure in which horizontal electrode layers and insulating layers are alternately stacked, then performing etching to form trenches and separated three-dimensional strip electrodes, next filling the trenches with an insulating medium, and then forming small holes at the boundary region between the three-dimensional strip electrodes and the insulating medium, thereafter sequentially depositing a phase change material on the walls of the small holes, and filling the small holes with an electrode material to prepare vertical electrodes, so as to obtain a three-dimensional stacked phase change memory stacked in multiple layers. By improving the overall process of the preparation method, the disclosure realizes the establishment of a three-dimensional phase change memory array by using a vertical electrode structure.
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公开(公告)号：US20210280784A1
公开(公告)日：2021-09-09
申请号：US16626520
申请日：2018-11-29
Inventor： Xiangshui MIAO , Hao TONG , Yushan SHEN , Wang CAI
Abstract: A three-dimensional stacked phase change memory and a preparation method thereof are provided. The method comprises: preparing first horizontal electrodes spaced apart from each other on a substrate; preparing first strip-shaped phase change layers, each having a central gap, between the first horizontal electrodes; preparing first selectors in the central gaps of the first strip-shaped phase change layers; preparing a first insulating layer; preparing second strip-shaped phase change layers at same vertical positions on the first insulating layer; preparing second selectors; then preparing horizontally-oriented insulating holes between the horizontal electrodes; and preparing vertical electrodes between the adjacent insulating holes, thereby forming a multilayer stacked phase change memory with a vertical structure.
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公开(公告)号：US20210242280A1
公开(公告)日：2021-08-05
申请号：US17042954
申请日：2019-07-12
Inventor： Hao TONG , Da HE , Xiangshui MIAO
Abstract: A pretreatment method of a selector device is provided, which includes: (1) performing a first voltage scan of a selector through selecting a voltage scan range and setting a first limit current Icc1 to obtain a resistance state R1 of a sub-threshold region thereof; (2) setting an nth limit current Icc(n) and performing an nth voltage scan of the selector according to a resistance state Rn-1 of a sub-threshold region of the selector after an n-1th voltage scan to obtain a resistance state Rn of a sub-threshold region thereof, where, Icc(n-1)
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公开(公告)号：US20210090646A1
公开(公告)日：2021-03-25
申请号：US16971678
申请日：2019-07-02
Inventor： Xiangshui MIAO , Yi LI , Xiaodi HUANG
Abstract: The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.
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40.发明申请公开(公告)号：US20200379276A1
公开(公告)日：2020-12-03
申请号：US16764403
申请日：2018-06-07
Inventor： Xiangshui MIAO , Yitao LU , Hao TONG , Yi WANG
Abstract: Disclosed in the present invention are a chalcogenide phase change material based all-optical switch and a manufacturing method therefor, relating to the field of optical communications. The all-optical switch comprises: stacked in sequence, a cover layer film, a chalcogenide phase change material film, an isolation layer film, a silicon photonic crystal, and a substrate. The silicon photonic crystal comprises a nano-porous structure such that the silicon photonic crystal has a Fano resonance effect. When the all-optical switch is used, the state of the chalcogenide phase change material film is controlled by means of laser, and the resonance state of the silicon photonic crystal is modulated to implement modulation of signal light transmissivity; the modulation range is within a communication band from 1500 nm to 1600 nm, thereby implementing an optical switch. The all-optical switch of the present invention has the characteristics of high contrast ratio, high rate and low loss.
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