公开(公告)号：US20170170307A1

公开(公告)日：2017-06-15

申请号：US15187485

申请日：2016-06-20

Applicant: Hyundai Motor Company

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  Nackyong Joo ,  Junghee Park ,  Jong Seok Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L29/7805 ,  H01L21/047 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7813

Abstract: A semiconductor device is provided. The device includes an n− type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n− type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n− type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n− type layer disposed therein.

公开(公告)号：US09490337B2

公开(公告)日：2016-11-08

申请号：US15051023

申请日：2016-02-23

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L29/66068 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7813

Abstract: A semiconductor device includes: a plurality of n type pillar regions and an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region.

公开(公告)号：US09391167B1

公开(公告)日：2016-07-12

申请号：US14944950

申请日：2015-11-18

Applicant: Hyundai Motor Company

Inventor： Youngkyun Jung ,  Junghee Park ,  Dae Hwan Chun ,  JongSeok Lee

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/16 ,  H01L29/417

CPC classification number: H01L29/66734 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236

Abstract: A method for manufacturing a semiconductor device includes: forming sequentially an n− type epitaxial layer and an n+ type area on a first surface of an n+ type silicon carbide substrate; forming a plurality of first trenches and a plurality of second trenches by etching the n− type epitaxial layer and the n+ type area using a first mask pattern as a mask after forming the first mask pattern on the n+ type area; forming a groove by etching the first mask pattern using a first photosensitive film pattern as a mask after forming the first photosensitive film pattern in the plurality of first trenches; forming a p type area by injecting p ions in the plurality of second trenches using the first mask pattern with the groove as the mask after removing the first photosensitive film pattern; forming a gate insulating layer in the plurality of first trenches after removing the first mask pattern with the groove; forming a gate electrode on the gate insulating layer; forming a passivation layer on the gate electrode; forming a source electrode in the plurality of second trenches; and forming a drain electrode on a second surface which is an opposite side to the first surface of the n+ type silicon carbide substrate.

Abstract translation: 一种制造半导体器件的方法包括：在n +型碳化硅衬底的第一表面上依次形成n型外延层和n +型区域; 通过在n +型区域上形成第一掩模图案之后，使用第一掩模图案作为掩模蚀刻n型外延层和n +型区域，形成多个第一沟槽和多个第二沟槽; 通过在所述多个第一沟槽中形成所述第一感光膜图案之后，使用第一感光膜图案作为掩模蚀刻所述第一掩模图案来形成沟槽; 通过在去除第一感光膜图案之后，使用具有沟槽作为掩模的第一掩模图案，在多个第二沟槽中注入p离子来形成p型区域; 在用所述槽除去所述第一掩模图案之后，在所述多个第一沟槽中形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 在栅电极上形成钝化层; 在所述多个第二沟槽中形成源电极; 以及在与n +型碳化硅衬底的第一表面相反的一侧的第二表面上形成漏电极。

公开(公告)号：US09299782B2

公开(公告)日：2016-03-29

申请号：US14025789

申请日：2013-09-12

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L31/0312 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L29/66068 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7813

Abstract: A semiconductor device includes: a plurality of n type pillar regions and an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region.

Abstract translation: 半导体器件包括：n +型碳化硅衬底的第一表面上的多个n型支柱区域和n型外延层; p型外延层和n +区，设置在所述多个n型支柱区域和所述n型外延层上; 穿过n +区的沟槽和p型外延层，并且设置在多个n型支柱区域和n型外延层上; 设置在所述沟槽内的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 设置在栅电极上的氧化膜; 设置在p型外延层上的源电极，n +区和氧化膜; 以及设置在n +型碳化硅衬底的第二表面上的漏电极，其中沟槽的每个拐角部分与相应的n型柱状区域接触。

公开(公告)号：US20150187883A1

公开(公告)日：2015-07-02

申请号：US14468819

申请日：2014-08-26

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Dae Hwan Chun ,  Kyoung-Kook Hong ,  Junghee Park ,  Youngkyun Jung

IPC: H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/512 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; an n+ region disposed on the second n− type epitaxial layer; a trench passing through the second n− type epitaxial layer, the p type epitaxial layer, and the n+ region, and disposed on the first n− type epitaxial layer; a p+ region disposed on the p type epitaxial layer and separated from the trench; and a gate insulating layer positioned in the trench, in which channels are disposed in the second n− type epitaxial layer of both sides of the trench and the p type epitaxial layer of both sides of the trench.

Abstract translation: 半导体器件包括：设置在n +型碳化硅衬底的第一表面上的第一n-型外延层; 设置在第一n型外延层上的p型外延层; 设置在p型外延层上的第二n型外延层; 设置在所述第二n型外延层上的n +区; 通过第二n型外延层的沟槽，p型外延层和n +区，并且设置在第一n型外延层上; 设置在p型外延层上并与沟槽分离的p +区; 以及定位在沟槽中的栅绝缘层，其中通道设置在沟槽两侧的第二n型外延层和沟槽两侧的p型外延层。

公开(公告)号：US08901572B2

公开(公告)日：2014-12-02

申请号：US14104974

申请日：2013-12-12

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813

Abstract: A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate.

Abstract translation: 半导体器件包括n +型碳化硅衬底; 设置在n +型碳化硅衬底的第一表面上的多个n型支柱区域，多个p型支柱区域和n型外延层; 顺序地设置在n型外延层上的p型外延层和n +区; 穿过n +区和p型外延层并设置在n型外延层上的沟槽; 设置在所述沟槽内的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 设置在栅电极上的氧化膜; 设置在p型外延层上的源电极，n +区和氧化膜; 以及位于n +型碳化硅衬底的第二表面上的漏电极。

公开(公告)号：US12262546B2

公开(公告)日：2025-03-25

申请号：US17835367

申请日：2022-06-08

Applicant: HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

Inventor： NackYong Joo ,  Dae Hwan Chun ,  Jungyeop Hong ,  Youngkyun Jung ,  Junghee Park

IPC: H10D12/00 ,  H02M1/088 ,  H02M7/537 ,  H10D62/17 ,  H10D64/23

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

公开(公告)号：US12027517B2

公开(公告)日：2024-07-02

申请号：US17569040

申请日：2022-01-05

Applicant: HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

Inventor： Jungyeop Hong ,  Dae Hwan Chun ,  NackYong Joo ,  Youngkyun Jung ,  Junghee Park

IPC: H01L27/06 ,  H01L21/82 ,  H01L21/8258 ,  H01L29/24

CPC classification number: H01L27/0688 ,  H01L21/8258 ,  H01L29/24

Abstract: Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga2O3) and the other includes silicon (Si).

公开(公告)号：US20200185496A1

公开(公告)日：2020-06-11

申请号：US16458454

申请日：2019-07-01

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n− type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

公开(公告)号：US10559701B2

公开(公告)日：2020-02-11

申请号：US16172647

申请日：2018-10-26

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/808 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/36

Abstract: A semiconductor device is provide. The device includes a first n− type of layer, a second n− type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n− type of layer, a p type of region is disposed between the second n− type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n− type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n− type of layer.