公开(公告)号：US12230697B2

公开(公告)日：2025-02-18

申请号：US17663866

申请日：2022-05-18

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： NackYong Joo ,  Dae Hwan Chun ,  Jungyeop Hong ,  Youngkyun Jung ,  Junghee Park

IPC: H01L29/739 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes an N+ type substrate, an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N− type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

公开(公告)号：US20190341504A1

公开(公告)日：2019-11-07

申请号：US16165885

申请日：2018-10-19

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： NackYong Joo ,  Youngkyun Jung ,  Junghee Park ,  JongSeok Lee ,  Dae Hwan Chun

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/47

Abstract: A semiconductor device may include an n− type of layer disposed at a first surface of a substrate; a p− type of region and a p+ type of region disposed at a top portion of the n− type of layer; a first electrode disposed on the p− type of region and the p+ type of region; and a second electrode disposed at a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p− type of region and a second metal layer disposed on the first metal layer, and the first metal layer is in continuous contact with the p− type of region.

公开(公告)号：US20190334036A1

公开(公告)日：2019-10-31

申请号：US16172647

申请日：2018-10-26

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/808 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is provide. The device includes a first n− type of layer, a second n− type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n− type of layer, a p type of region is disposed between the second n− type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n− type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n− type of layer.

公开(公告)号：US10249732B1

公开(公告)日：2019-04-02

申请号：US15823856

申请日：2017-11-28

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Youngkyun Jung ,  NackYong Joo ,  Junghee Park ,  Hyun Woo Noh ,  JongSeok Lee ,  Dae Hwan Chun

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device is provided. The method includes sequentially forming an n− type of layer, a p type of region, and an n+ type of region on a first surface of a substrate, forming a preliminary trench in the n− type of layer by a first etching process and forming a preliminary gate insulating layer by a first thermal oxidation process. The method includes etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by a second etching process and forming a gate insulating layer in the trench by a second thermal oxidation process. The gate insulating layer includes a first and second portion. The preliminary first portion is thicker than the preliminary second portion and the first portion. The first portion thickness is equal to the thickness of the second portion.

公开(公告)号：US10115794B2

公开(公告)日：2018-10-30

申请号：US15363892

申请日：2016-11-29

Applicant: HYUNDAI MOTOR COMPANY ,  Hyundai Autron Co., Ltd.

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  JongSeok Lee ,  Youngjoon Kim ,  Taeyeop Kim ,  Hyuk Woo

IPC: H01L29/94 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n− type layer; a p type region disposed on both side surfaces of the first trench; an n+ type region disposed on both side surfaces of the first trench and disposed on the n− type layer and the p type region; a gate insulating layer disposed inside the first trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ region; and a drain electrode disposed on the second surface of the n+ type silicon carbide substrate, wherein a first channel as an accumulation layer channel and a second channel as an inversion layer channel are disposed in both side surfaces of the first trench, and the first channel and the second channel are disposed to be adjacent in a horizontal direction for the first surface of the n+ type silicon carbide substrate.

公开(公告)号：US09997624B2

公开(公告)日：2018-06-12

申请号：US15348613

申请日：2016-11-10

Applicant: HYUNDAI MOTOR COMPANY

Inventor： NackYong Joo ,  Youngkyun Jung ,  Junghee Park ,  JongSeok Lee ,  Dae Hwan Chun

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/16 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A semiconductor device includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n− type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n− type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

公开(公告)号：US20180108774A1

公开(公告)日：2018-04-19

申请号：US15377708

申请日：2016-12-13

Applicant: Hyundai Motor Company

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  NackYong Joo ,  Junghee Park ,  JongSeok Lee

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/7827 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66666

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.

公开(公告)号：US20150183063A1

公开(公告)日：2015-07-02

申请号：US14469031

申请日：2014-08-26

Applicant: Hyundai Motor Company

Inventor： Kyoung-Kook Hong ,  Youngkyun Jung ,  Jong Seok Lee ,  Dae Hwan Chun ,  Su Bin Kang

IPC: B23K35/30 ,  B23K35/02 ,  B22F3/00

CPC classification number: B23K35/3006 ,  B22F1/0085 ,  B22F1/0096 ,  B22F3/00 ,  B22F2998/10 ,  B23K35/025 ,  C22C1/0466 ,  B22F1/0003 ,  B22F1/025

Abstract: A method of joining silver paste is provided. The method includes preparing silver paste comprising silver powders and lead powders and heating silver paste. The silver powders are then joined.

Abstract translation: 提供了一种接合银膏的方法。 该方法包括制备包含银粉和铅粉的银膏并加热银浆。 然后将银粉末接合。

公开(公告)号：US09029872B2

公开(公告)日：2015-05-12

申请号：US14098409

申请日：2013-12-05

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L21/00 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/04 ,  H01L29/417

CPC classification number: H01L29/1608 ,  H01L21/0455 ,  H01L29/0623 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813

Abstract: The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate.A semiconductor device according to the present inventive concept includes a p type pillar region disposed below the trench, spaced apart from the trench or a first p type pillar region and a second p type pillar region disposed below the trench and corresponding to two corners of the trench.

Abstract translation: 本发明构思是为了改善使用沟槽栅极的碳化硅MOSFET的击穿电压。 根据本发明构思的半导体器件包括设置在沟槽下方的与沟槽间隔开的p型柱状区域或设置在沟槽下方并对应于沟槽的两个角的第一p型柱状区域和第二p型支柱区域 。

公开(公告)号：US09006746B2

公开(公告)日：2015-04-14

申请号：US14143649

申请日：2013-12-30

Applicant: Hyundai Motor Company

Inventor： Youngkyun Jung ,  Dae Hwan Chun ,  Kyoung-Kook Hong ,  Jong Seok Lee ,  Junghee Park

IPC: H01L29/161 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606

Abstract: A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n− type epitaxial layer. An n+ type epitaxial layer is disposed on the n− type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n− type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n− type epitaxial layer and substantially curved parts that extend from the substantially straight parts.

Abstract translation: 提供肖特基势垒二极管和制造二极管的方法。 二极管包括设置在n +型碳化硅衬底的第一表面上的n型外延层和设置在n型外延层内的多个p +区。 在n型外延层上设置n +型外延层，在n +型外延层上设置肖特基电极，在n +型碳化硅基板的第二面上设置欧姆电极。 n +型外延层包括设置在n型外延层上的多个柱部分和设置在柱部分之间并暴露p +区域的多个开口。 每个支柱部分包括接触n型外延层的基本上直的部分和从基本上直的部分延伸的基本上弯曲的部分。