公开(公告)号：US09310911B2

公开(公告)日：2016-04-12

申请号：US14234950

申请日：2012-07-27

申请人： Yasuhiro Sugita ,  Kazutoshi Kida ,  Shinji Yamagishi ,  Yuhji Yashiro ,  Hiroyuki Ogawa ,  Shigeyasu Mori ,  Seiji Kaneko ,  Yasuyuki Ogawa ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru

发明人： Yasuhiro Sugita ,  Kazutoshi Kida ,  Shinji Yamagishi ,  Yuhji Yashiro ,  Hiroyuki Ogawa ,  Shigeyasu Mori ,  Seiji Kaneko ,  Yasuyuki Ogawa ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru

IPC分类号： G06F3/041 ,  G09G5/00 ,  G06F3/042 ,  G06F3/044 ,  G09G3/36

CPC分类号： G06F3/041 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/3648 ,  G09G2356/00

摘要： A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.

摘要翻译： 包括在显示部分中的多个像素的每一个中的有源元件的半导体层由包含选自由In，Ga和Zn组成的组中的至少一种元素的氧化物层构成。 对于显示部分，提供一种被配置为执行控制的液晶面板的定时控制器（13），使得（i）写入图像数据的第一周期的长度不超过第二周期的两倍 和/或（ii）一（1）个帧周期长于16.7毫秒。

公开(公告)号：US08704819B2

公开(公告)日：2014-04-22

申请号：US13989486

申请日：2012-08-29

申请人： Yasuyuki Ogawa ,  Seiji Kaneko ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

发明人： Yasuyuki Ogawa ,  Seiji Kaneko ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

IPC分类号： G09G5/00

CPC分类号： G06F1/3265 ,  G09G3/3618 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/08

摘要： There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same. A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, the screen refreshing is performed by reading video data stored in the frame memory (36).

摘要翻译： 提供了一种显示装置，其能够基于发送的命令中包括的视频数据，以低功耗显示几乎不变化的图像，并且还提供了一种用于驱动该图像的方法。 显示定时控制器（31）确定每个帧周期是否外部发送的命令包括更新的视频数据。 结果，当确定不包括更新的视频数据时，通过不读取存储在帧存储器（36）中的视频数据来暂停屏幕刷新。 此外，当确定包括更新的视频数据时，通过读取存储在帧存储器（36）中的视频数据来执行屏幕刷新。

公开(公告)号：US08686990B2

公开(公告)日：2014-04-01

申请号：US13885101

申请日：2012-04-02

申请人： Kaoru Yamamoto

发明人： Kaoru Yamamoto

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3677 ,  G09G2230/00 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184 ,  G11C19/28

摘要： Provided is a monolithic gate driver capable of performing block-reversal driving without causing deterioration of display quality or an increase in power consumption. Gate bus lines are divided into z blocks. Agate driver (400) is provided with a block scanning circuit (40), as well as odd-numbered line scanning circuits (42) each provided for each block and even-numbered line scanning circuits (44) each provided for each block. The block scanning circuit (40) sequentially selects the first to z-th blocks one by one, and alternately selects the odd-numbered line scanning circuits (42) and the even-numbered line scanning circuits (44). Each of the odd-numbered line scanning circuits (42) sequentially and selectively drives the odd-numbered gate bus lines included in the corresponding block. Each of the even-numbered line scanning circuits (44) sequentially and selectively drives the even-numbered gate bus lines included in the corresponding block.

摘要翻译： 提供了能够执行块反转驱动而不会导致显示质量劣化或功耗增加的单片栅极驱动器。 栅极总线分为z区。 玛瑙驱动器（400）设置有块扫描电路（40），以及为每个块提供的奇数行扫描电路（42），并且为每个块提供每个块和偶数行扫描电路（44）。 块扫描电路（40）逐个顺序选择第一至第Z块，并交替地选择奇数行扫描电路（42）和偶数行扫描电路（44）。 奇数行扫描电路（42）中的每一个依次选择性地驱动包括在相应块中的奇数编号的栅极总线。 每个偶数行扫描电路（44）顺序选择性地驱动包括在相应块中的偶数栅极总线。

公开(公告)号：US08665408B2

公开(公告)日：2014-03-04

申请号：US13992523

申请日：2011-12-01

申请人： Kaoru Yamamoto

发明人： Kaoru Yamamoto

IPC分类号： G02F1/1345

CPC分类号： G02F1/1365 ,  G02F1/134309 ,  G02F2001/134318 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2310/0205

摘要： A liquid crystal display device (100) according to the present invention includes a first substrate (10) including pixel electrodes (11), gate lines (G) and switching elements (12), a second substrate (20) including a plurality of signal electrodes (21) which are electrically independent of each other, and a liquid crystal layer (30) interposed between the first and second substrates. The first substrate further includes a gate driver (15) which generates gate signals to be supplied to the gate lines. The second substrate further includes an external connecting terminal section (24). A signal that has been input through the external connecting terminal section is supplied to the gate driver. The present invention provides a liquid crystal display device with a counter source structure which contributes to narrowing its frame area.

摘要翻译： 根据本发明的液晶显示装置（100）包括：包括像素电极（11），栅极线（G）和开关元件（12）的第一基板（10），包括多个信号的第二基板 彼此电独立的电极（21）和置于第一和第二基板之间的液晶层（30）。 第一衬底还包括栅极驱动器（15），其产生要提供给栅极线的栅极信号。 第二基板还包括外部连接端子部分（24）。 已经通过外部连接端子部分输入的信号被提供给栅极驱动器。 本发明提供了一种具有反向源结构的液晶显示装置，其有助于缩小其框架面积。

公开(公告)号：US20140022234A1

公开(公告)日：2014-01-23

申请号：US13989486

申请日：2012-08-29

申请人： Yasuyuki Ogawa ,  Seiji Kaneko ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

发明人： Yasuyuki Ogawa ,  Seiji Kaneko ,  Kaoru Yamamoto ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

IPC分类号： G06F1/32 ,  G09G3/36

CPC分类号： G06F1/3265 ,  G09G3/3618 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/08

摘要： There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same.A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, screen refreshing is performed by reading video data stored in the frame memory (36).

摘要翻译： 提供了一种显示装置，其能够基于发送的命令中包括的视频数据，以低功耗显示几乎不变化的图像，并且还提供了一种用于驱动该图像的方法。 显示定时控制器（31）确定每个帧周期是否外部发送的命令包括更新的视频数据。 结果，当确定不包括更新的视频数据时，通过不读取存储在帧存储器（36）中的视频数据来暂停屏幕刷新。 此外，当确定包括更新的视频数据时，通过读取存储在帧存储器（36）中的视频数据来执行屏幕刷新。

公开(公告)号：US20130120331A1

公开(公告)日：2013-05-16

申请号：US13810773

申请日：2011-07-26

申请人： Kaoru Yamamoto ,  Yasuhiro Sugita ,  Kohei Tanaka

发明人： Kaoru Yamamoto ,  Yasuhiro Sugita ,  Kohei Tanaka

IPC分类号： G06F3/03

CPC分类号： G06F3/0304 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/042 ,  G09G3/3406 ,  G09G2310/0237 ,  G09G2360/145

摘要： A sensor pixel circuit (9) includes: a light receiving element (PD); a first node Vsig that retains charges corresponding to an amount of light incident on the light receiving element; and a second node Vint that receives charges from the first nodeVsig and retains the charges. Under control by a driving circuit (7), during one of a detection period while a light source (3) for sensors is in an ON state and a detection period while the light source (3) for sensors is in an OFF state, charges corresponding to an amount of light incident on the light receiving element (PD) during this detection period are accumulated in the first node Vsig. The charges accumulated are transferred from the first node Vsig to the second node Vint. During the other one of the detection period while the light source for sensors is in the ON state and the detection period while the light source for sensors is in the OFF state, charges corresponding to an amount of light incident on the light receiving element (PD) during this detection period are accumulated in the first node Vsig, and the charges accumulated are transferred from the first node Vsig to the second node Vint. By doing so, a value of a difference between the amount of light accumulated while the light source for sensors is in the ON state and the amount of light accumulated while the light source for sensors is in the OFF state is determined in the second node Vint.

摘要翻译： 传感器像素电路（9）包括：光接收元件（PD）; 保持对应于入射在光接收元件上的光量的电荷的第一节点Vsig; 以及从第一节点Vsig接收电荷并保持电荷的第二节点Vint。 在驱动电路（7）的控制下，在用于传感器的光源（3）处于接通状态的检测期间和传感器的光源（3）处于关闭状态的检测期间的一个中， 对应于在该检测期间入射到受光元件（PD）上的光量在第一节点Vsig中被累积。 累积的电荷从第一节点Vsig传送到第二节点Vint。 在传感器的光源处于接通状态的检测期间的另一个中，以及传感器的光源处于截止状态的检测期间，对应于入射到受光元件（PD）上的光量 ）累积在第一节点Vsig中，并且积累的电荷从第一节点Vsig传送到第二节点Vint。 通过这样做，在第二节点Vint中确定在传感器的光源处于ON状态时累积的光量与传感器的光源之间的累积光量处于OFF状态之间的差值 。

公开(公告)号：US20120176357A1

公开(公告)日：2012-07-12

申请号：US13497383

申请日：2010-06-08

申请人： Hiromi Katoh ,  Yasuhiro Sugita ,  Kohhei Tanaka ,  Kaoru Yamamoto ,  Naru Usukura ,  Hiroaki Shigeta

发明人： Hiromi Katoh ,  Yasuhiro Sugita ,  Kohhei Tanaka ,  Kaoru Yamamoto ,  Naru Usukura ,  Hiroaki Shigeta

IPC分类号： G06F3/038

CPC分类号： G06F3/0412 ,  G06F3/0418 ,  G06F3/042 ,  G09G3/3406 ,  G09G2360/144 ,  G09G2360/148

摘要： A plurality of first and second sensor pixel circuits each sensing light during a designated sensing period and retaining the amount of sensed light otherwise are arranged in a pixel region. A backlight is turned on once for a predetermined time in one-frame period. A sensing period when the backlight is turned on and a sensing period when the backlight is turned off are set once, respectively, in the one-frame period. The first sensor pixel circuit is reset. The second sensor pixel circuit is reset. Read from sensor pixel circuits of two types is performed in parallel in a line sequential manner during a period other than the periods and. A difference circuit provided outside of the sensor pixel circuits is used for obtaining a difference between an amount of light when the backlight is turned on and an amount of light when the backlight is turned off.

摘要翻译： 多个第一和第二传感器像素电路在指定的检测周期期间感测光并保持感测光的量，否则布置在像素区域中。 背光源在一帧周期内打开一段预定时间。 在一帧期间分别设定背光源开启的感测期间和背光源关闭时的感测期间一次。 第一传感器像素电路被复位。 第二传感器像素电路被复位。 从周期和周期以外的期间以线顺序的方式并行地进行两种类型的传感器像素电路的读取。 设置在传感器像素电路外部的差分电路用于获得当背光打开时的光量与背光被关闭时的光量之间的差。

公开(公告)号：US20100236480A1

公开(公告)日：2010-09-23

申请号：US12680041

申请日：2008-09-22

申请人： Masamichi Hara ,  Atsushi Gomi ,  Shinji Maekawa ,  Kaoru Yamamoto ,  Satoshi Taga

发明人： Masamichi Hara ,  Atsushi Gomi ,  Shinji Maekawa ,  Kaoru Yamamoto ,  Satoshi Taga

IPC分类号： C23C16/54 ,  F15D1/00

CPC分类号： C23C16/4481 ,  Y10T137/8158 ,  Y10T137/8376

摘要： A raw material gas supply system (6) supplies a raw material gas to a gas use system (2) kept in a reduced pressure atmosphere. The system includes: a raw material tank (40) for storing a liquid raw material or a solid raw material; a raw material conduit (46) connected at one end to the raw material tank and connected at the other end to the gas use system; a carrier gas supply mechanism (54), connected to the raw material tank, for supplying a carrier gas into the raw material tank while controlling the flow rate of the gas; on-off valves (48, 50) interposed in the raw material conduit; a heater (64) for heating the raw material conduit and the on-off valves; and a temperature control device (92) for controlling the heater, wherein the raw material conduit and the on-off valves are each formed of a metal material having good thermal conductivity.

摘要翻译： 原料气体供给系统（6）向保持在减压气氛中的气体使用系统（2）供给原料气体。 该系统包括：原料罐（40），用于储存液体原料或固体原料; 原料管道（46），其一端连接到原料罐，并在另一端连接到气体使用系统; 连接到原料罐的载气供给机构（54），用于在控制气体的流量的同时向载体气体供给载气; 开闭阀（48,50）插入在原料管道中; 用于加热原料管道和开关阀的加热器（64）; 以及用于控制加热器的温度控制装置（92），其中原料管道和开关阀均由具有良好导热性的金属材料形成。

公开(公告)号：US20100210115A1

公开(公告)日：2010-08-19

申请号：US12722193

申请日：2010-03-11

申请人： Masamichi HARA ,  Atsushi Gomi ,  Shinji Maekawa ,  Satoshi Taga ,  Kaoru Yamamoto

发明人： Masamichi HARA ,  Atsushi Gomi ,  Shinji Maekawa ,  Satoshi Taga ,  Kaoru Yamamoto

IPC分类号： H01L21/477 ,  H05B3/68

CPC分类号： H01L21/67103 ,  C23C16/4586 ,  C23C16/52 ,  H01L21/67109

摘要： A substrate mounting mechanism on which a target substrate is placed is provided. The substrate mounting mechanism includes a heater plate, which has a substrate mounting surface on which the target substrate is placed and has a heater embedded therein to heat the substrate to a deposition temperature at which a film is deposited. The substrate mounting mechanism also includes a temperature control jacket, which is formed to cover at least a surface of the heater plate other than the substrate mounting surface and adjusts the temperature to a non-deposition temperature below the deposition temperature.

摘要翻译： 设置放置目标基板的基板安装机构。 基板安装机构包括加热板，该加热板具有放置目标基板的基板安装表面，并且嵌入有加热器，以将基板加热到沉积膜的沉积温度。 衬底安装机构还包括温度控制护套，其形成为覆盖加热器板的除了衬底安装表面之外的至少一个表面，并将温度调节到低于沉积温度的非沉积温度。

公开(公告)号：US20090046514A1

公开(公告)日：2009-02-19

申请号：US12094379

申请日：2006-11-01

申请人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G11C11/34

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。