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    Analog-to-digital converter including differential pair circuit
    31.
    发明授权
    Analog-to-digital converter including differential pair circuit 失效
    模数转换器包括差分对电路

    公开(公告)号：US08681033B2

    公开(公告)日：2014-03-25

    申请号：US13535118

    申请日：2012-06-27

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

    摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

    ANALOG-TO-DIGITAL CONVERTER
    32.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 失效
    模拟数字转换器

    公开(公告)号：US20130076550A1

    公开(公告)日：2013-03-28

    申请号：US13536085

    申请日：2012-06-28

    申请人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H01L27/22 ,  H01L43/08 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

    摘要翻译： 根据实施例，模数转换器包括电压产生单元和多个比较器。 电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。 多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。 多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

    Spin transistor and magnetic memory
    33.
    发明授权
    Spin transistor and magnetic memory 有权
    旋转晶体管和磁存储器

    公开(公告)号：US07956395B2

    公开(公告)日：2011-06-07

    申请号：US12200169

    申请日：2008-08-28

    申请人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    发明人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    IPC分类号： H01L27/115

    CPC分类号： H01L29/66984 ,  B82Y25/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3286

    摘要： A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.

    摘要翻译： 自旋晶体管包括设置在基板上并具有不变磁化方向的第一铁磁层，在第一方向上设置在与第一铁磁层隔开的基板上并具有可变磁化方向的第二铁磁层，多个突出半导体 设置在基板上以在第一方向上延伸并夹在第一铁磁层和第二铁磁层之间的层，分别设置在突出半导体层中的多个沟道区和设置在沟道区上的栅电极。

    Semiconductor integrated circuit
    40.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08111087B2

    公开(公告)日：2012-02-07

    申请号：US12408953

    申请日：2009-03-23

    申请人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    发明人： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

    IPC分类号： H03K19/094

    CPC分类号： G11C14/0081 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/02 ,  G11C2213/31 ,  G11C2213/32 ,  H03K19/0944 ,  H03K19/18

    摘要： A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

    摘要翻译： 半导体集成电路包括包括磁性隧道结和磁半导体结之一的n沟道自旋FET，所述n沟道自旋FET包括用于接收输入信号的栅极端子，用于接收第一电源的源极端子 电位和连接到输出端的漏极端子，包括用于接收时钟信号的栅极端子的p沟道FET，用于接收第二电源电位的源极端子和连接到输出端子的漏极端子，后续 连接到输出端子的电路，以及控制电路，其导通p沟道FET以开始对输出端子充电，然后关闭p沟道FET以结束充电，并将输入信号提供给 n沟道自旋FET。