公开(公告)号：US06540410B2

公开(公告)日：2003-04-01

申请号：US09739187

申请日：2000-12-18

申请人： Darrell R. Childers ,  Hieu Tran ,  Eric W. Kent

发明人： Darrell R. Childers ,  Hieu Tran ,  Eric W. Kent

IPC分类号： G02B636

CPC分类号： G02B6/3897 ,  G02B6/3821 ,  G02B6/3869 ,  G02B6/3893

摘要： A fiber optic connector for mounting on a panel comprises an outer housing defining an interior passage extending longitudinally therethrough, and at least one mounting element connected with the outer housing for mounting the connector onto the panel. The connector also includes a connector insert subassembly inserted through the rear end of the outer housing into the interior passage thereof. The connector insert subassembly is slidable longitudinally within the outer housing, and comprises an inner housing defining an inner passage extending longitudinally therethrough, and a ferrule holder and ferrule mounted within the inner passage of the inner housing. A compression spring is inserted into the rear end of the outer housing abutting the connector insert subassembly, and a spring retainer is inserted into the outer housing behind the compression spring to capture the spring in a compressed condition so as to cause the spring to bias the connector insert subassembly forwardly against a stop defined by the outer housing.

公开(公告)号：US20120265667A1

公开(公告)日：2012-10-18

申请号：US13449310

申请日：2012-04-17

申请人： Thomas Sachson ,  Hieu Tran

发明人： Thomas Sachson ,  Hieu Tran

IPC分类号： G06Q40/04

CPC分类号： G06Q40/04

摘要： The Financial Instrument Discovery, Transparency, Communication, and Trading Facilitation invention allows parties to virtualize prospective and existing financial instruments (including derivative and other analogous complex financial instruments) into one or more computer software applications via a user authoring software toolkit, and to upload such one or more virtualized instrument to a cloud hosting environment (or analogous online storage ecosystem) for further sharing of such virtualized instruments with interested parties over a communications network where other market participants may engage with the cloud hosting environment and search for, download, and review such virtualized instruments. Further, the Invention allows for downloading parties and authors to communicate directly and to do such “peer to peer” communications on an anonymous, partially anonymous, or non-anonymous basis, and have such communications be secure and/or encrypted.

摘要翻译： 金融工具发现，透明度，沟通和交易促进发明允许各方通过用户创作软件工具包将预期和现有的金融工具（包括衍生产品和其他类似的复杂金融工具）虚拟化为一个或多个计算机软件应用程序，并将其上传 一个或多个虚拟化仪器到云托管环境（或类似的在线存储生态系统），用于通过通信网络进一步与感兴趣的方面共享这样的虚拟化仪器，其他市场参与者可以与云托管环境进行互动，并搜索，下载和检查 这样的虚拟化仪器。 此外，本发明允许下载方和作者直接进行通信，并以匿名，部分匿名或非匿名的方式进行这种对等通信，并且具有这样的通信是安全和/或加密的。

公开(公告)号：US20070070753A1

公开(公告)日：2007-03-29

申请号：US11602873

申请日：2006-11-20

申请人： Hieu Tran

发明人： Hieu Tran

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.

公开(公告)号：US20060088247A1

公开(公告)日：2006-04-27

申请号：US10971884

申请日：2004-10-22

申请人： Hieu Tran ,  Xin Liu ,  James Luther ,  Thomas Theuerkorn ,  Charles Yow

发明人： Hieu Tran ,  Xin Liu ,  James Luther ,  Thomas Theuerkorn ,  Charles Yow

IPC分类号： G02B6/38

CPC分类号： G02B6/3874

摘要： A one-piece fiber optic receptacle is provided for aligning and optically connecting a plug ferrule with a back-side ferrule of like configuration. The fiber optic receptacle includes a receptacle housing defining an internal cavity opening through an external end and an opposed internal end, an alignment sleeve disposed within the internal cavity and received within the internal end of the receptacle housing, and a sleeve retainer secured to the internal end of the receptacle housing and operable for providing access to the alignment sleeve from the internal end of the receptacle housing. The alignment sleeve includes a chamfer for guiding the back-side ferrule into the alignment sleeve. The sleeve retainer has an opening and a plurality of alignment ribs disposed about the opening for permitting angular rotation of the alignment sleeve relative to the sleeve retainer during insertion of the plug ferrule and the back-side ferrule into the alignment sleeve.

摘要翻译： 提供一体式光纤插座，用于对准和光学连接插头套圈与类似结构的背面套圈。 光纤插座包括容纳壳体，其限定通过外部端部和相对的内部端部的内部空腔开口，配置套筒，其设置在内部空腔内并容纳在插座壳体的内部端部内，并且套筒保持器固定到内部 插座壳体的端部并且可操作以从插座壳体的内端提供对准套筒的接近。 对准套筒包括用于将后侧套圈引导到对准套筒中的倒角。 套筒保持器具有一个开口和多个排列的肋条，围绕该开口设置，用于允许对准套筒相对于套筒保持器的角度旋转，以将插头套圈和后侧套圈插入对准套筒中。

公开(公告)号：US20060072363A1

公开(公告)日：2006-04-06

申请号：US11283195

申请日：2005-11-18

申请人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

发明人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

IPC分类号： G11C7/02

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

公开(公告)号：US20060017084A1

公开(公告)日：2006-01-26

申请号：US10897045

申请日：2004-07-22

申请人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

发明人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/0805 ,  H01L27/0811 ,  H01L29/94

摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

公开(公告)号：US20050104116A1

公开(公告)日：2005-05-19

申请号：US10714243

申请日：2003-11-13

申请人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

发明人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US20080080817A1

公开(公告)日：2008-04-03

申请号：US11980938

申请日：2007-10-31

申请人： Stuart Melton ,  David Thompson ,  Michael Gimblet ,  Hieu Tran ,  Richard Wagman ,  Xin Liu

发明人： Stuart Melton ,  David Thompson ,  Michael Gimblet ,  Hieu Tran ,  Richard Wagman ,  Xin Liu

IPC分类号： G02B6/36

CPC分类号： G02B6/3849 ,  G02B6/3816 ,  G02B6/3873 ,  G02B6/3879 ,  G02B6/3887 ,  G02B6/3893 ,  G02B6/4429 ,  G02B6/4433 ,  G02B6/4471

摘要： A preconnectorized outdoor cable streamlines the deployment of optical waveguides into the last mile of an optical network. The preconnectorized outdoor cable includes a cable and at least one plug connector. The plug connector is attached to a first end of the cable, thereby connectorizing at least one optical waveguide. The cable has at least one optical waveguide, at least one tensile element, and a cable jacket. Various cable designs such as figure-eight or flat cables may be used with the plug connector. In preferred embodiments, the plug connector includes a crimp assembly having a crimp housing and a crimp band. The crimp housing has two half-shells being held together by the crimp band for securing the at least one tensile element. When fully assembled, the crimp housing fits into a shroud of the preconnectorized cable. The shroud aides in mating the preconnectorized cable with a complimentary receptacle.

摘要翻译： 预先连接的室外电缆可以将光波导的部署简化到光网络的最后一英里。 预连接器室外电缆包括电缆和至少一个插头连接器。 插头连接器附接到电缆的第一端，从而将至少一个光波导连接起来。 电缆具有至少一个光波导，至少一个拉伸元件和电缆护套。 诸如图八或扁平电缆的各种电缆设计可以与插头连接器一起使用。 在优选实施例中，插头连接器包括具有压接壳体和压接带的压接组件。 卷边壳体具有两个半壳，通过卷边带固定在一起，用于固定至少一个拉伸元件。 当完全组装时，压接壳体装配到预连接电缆的护罩中。 护罩可以将预连接电缆与互补的插座相配合。

公开(公告)号：US20070165436A1

公开(公告)日：2007-07-19

申请号：US11717922

申请日：2007-03-13

申请人： Vishal Sarin ,  Hieu Tran ,  Isao Nojima

发明人： Vishal Sarin ,  Hieu Tran ,  Isao Nojima

IPC分类号： G11C7/00 ,  G11C15/00 ,  G11C5/14 ,  G11C7/06

CPC分类号： G11C14/00 ,  G11C15/046

摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

公开(公告)号：US20070159904A1

公开(公告)日：2007-07-12

申请号：US11726913

申请日：2007-03-22

申请人： Hieu Tran ,  Sakhawat Khan

发明人： Hieu Tran ,  Sakhawat Khan

IPC分类号： G11C7/02

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

摘要翻译： 为数字多位非易失性存储器集成系统提供高速电压模式感测。 一个实施例具有本地源跟随器阶段，之后是高速公共源级。 另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。 另一个实施例具有公共源级，之后是源跟随器。 使用自动归零方案。 使用电容感测方案。 描述多级并行操作。