公开(公告)号：US08217883B2

公开(公告)日：2012-07-10

申请号：US11979714

申请日：2007-11-07

申请人： Junichiro Ishii ,  Hiroshi Tsuchi

发明人： Junichiro Ishii ,  Hiroshi Tsuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/027 ,  Y10T307/74 ,  Y10T307/747

摘要： Disclosed is an output circuit including a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.

摘要翻译： 公开了一种包括连接开关和操作单元的输出电路。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。

公开(公告)号：US20100013686A1

公开(公告)日：2010-01-21

申请号：US12458594

申请日：2009-07-16

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/00 ,  G11C27/02 ,  H03M1/66

CPC分类号： G11C27/024

摘要： Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal. The sampling voltage supply circuit delivers a sampling voltage to the one end of at least one of the first and second capacitance elements.

摘要翻译： 公开了一种采样保持电路，包括差分电路，放大器级和采样电压供应电路。 差分电路包括第一和第二电容元件，其电荷由第一开关分配，第一MOS晶体管具有通过第二开关连接到第一电容元件的一端的栅极，并且还经由第三开关连接到 输出端子，并且具有连接到第一电流源的源极，第二MOS晶体管，其栅极连接到第二电容元件的一端，并且具有连接到第二电流源的源极，并且还经由第四开关连接到源极 以及连接在第一和第二MOS晶体管的漏极和第二电源的端子之间的负载电路。 放大器级接收差分电路的输出，并具有连接到输出端子的输出。 采样电压供应电路将采样电压传送到第一和第二电容元件中的至少一个电容元件的一端。

公开(公告)号：US07595533B2

公开(公告)日：2009-09-29

申请号：US11740226

申请日：2007-04-25

申请人： Kenji Sera ,  Hiroshi Tsuchi

发明人： Kenji Sera ,  Hiroshi Tsuchi

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L27/127 ,  G11C7/062 ,  H01L27/1214 ,  H03F3/45192 ,  H03F3/45219 ,  H03K5/2481 ,  H03K19/0016

摘要： When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

摘要翻译： 当在形成在玻璃基板上的多晶硅膜上形成n沟道薄膜晶体管（TFT）和p沟道TFT时，包括其中P掺杂剂或N掺杂剂同时引入沟道的工艺 n沟道TFT的一部分的区域和p沟道TFT的一部分。 在单通道掺杂操作中，可以形成一组低VT和高VT p沟道TFT以及一组低VT和高VT n沟道TFT。 该方法用于形成高VT TFT，其可以减少逻辑和开关电路中的截止电流，并且用于形成低VT TFT，这可以扩大模拟电路中的动态范围，以提高薄膜的性能 半导体。

公开(公告)号：US07545305B2

公开(公告)日：2009-06-09

申请号：US11979342

申请日：2007-11-01

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： H03M1/742 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0291 ,  G09G2330/021

摘要： A data driver includes a positive-polarity reference voltage generation circuit that outputs positive-polarity reference voltages, a positive-polarity decoder that receives the positive-polarity reference voltages from the positive-polarity reference voltage generation circuit, end selects and outputs at least one positive-polarity reference voltage in accordance with first digital data, a positive-polarity amplifier which includes a first differential units that receives the selected reference voltage selected by the positive-polarity decoder, performs amplification, and outputs a voltage to a first amplifier output terminal, δ negative-polarity reference voltage generation circuit that outputs negative-polarity reference voltages, and a negative-polarity decoder that receives the negative-polarity reference voltages from the negative-polarity reference voltage generation circuit, and selects and outputs at least one negative-polarity reference voltage in accordance with second digital data.

摘要翻译： 数据驱动器包括正极参考电压产生电路，其输出正极性参考电压;正极性解码器，其从正极参考电压产生电路接收正极参考电压，结束选择并输出至少一个 根据第一数字数据的正极性参考电压，包括接收由正极性解码器选择的所选择的参考电压的第一差分单元的正极放大器进行放大，并将电压输出到第一放大器输出端子 输出负极性基准电压的δ负极性基准电压产生电路和从负极性基准电压产生电路接收负极性基准电压的负极性译码器，并选择并输出至少一个负极性参考电压， 根据第二di的极性参考电压 资料数据。

公开(公告)号：US07443239B2

公开(公告)日：2008-10-28

申请号：US11648530

申请日：2007-01-03

申请人： Hiroshi Tsuchi ,  Junichiro Ishii ,  Kouichi Nishimura

发明人： Hiroshi Tsuchi ,  Junichiro Ishii ,  Kouichi Nishimura

IPC分类号： H03F3/45

CPC分类号： H03F3/45233 ,  H03F2203/45726

摘要： A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

摘要翻译： 一种差分放大电路，其包括形成该差分对的负载电路的差分对和共源共栅电流镜电路。 共源共栅电流镜电路包括控制端耦合的第一晶体管对以及分别在耦合控制端接收第一和第二偏置信号的第二和第三晶体管对。 第二晶体管对直接连接在第一晶体管对与共源共栅电流镜电路的输入端和输出端之间，第三晶体管对交叉连接在第一晶体管对与输入端之间，输出端 的共源共栅电流镜电路。 通过改变第一和第二偏置信号的电压值来控制第二和第三晶体管对，以便各自通过改变第一和第二偏置信号的电压值而被置于有功和无效状态，其中控制是以这样的方式进行的：当这些晶体管对中的一个处于 活动状态，另一个处于非活动状态。

公开(公告)号：US07368990B2

公开(公告)日：2008-05-06

申请号：US11304599

申请日：2005-12-16

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  H03F2203/45504 ,  H03F2203/45521 ,  H03F2203/45616

摘要： Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively. The differential amplifier further includes a load circuit connected to output pairs of the first and second differential pairs for outputting a signal obtained on combining outputs of the first and second differential pairs from at least one of a pair of connection nodes between the output pairs of the first and second differential pairs and the load circuit, an amplifier stage supplied with at least one signal at a connection node of the output pairs of the first and second differential pairs and the load circuit to output a voltage at the output terminal, and a current control circuit controlling the first and second current sources for controlling the ratio of currents supplied to the first and second differential pairs.

摘要翻译： 公开了一种差分放大器，其包括第一和第二输入端子，输出端子，第一和第二差分对以及用于向第一和第二差分对提供电流的第一和第二电流源。 第一差分对具有分别连接到第一输入端和输出端的输入对的第一和第二输入。 第二差分对分别具有连接到第二输入端子和输出端子的输入对的第一和第二输入端。 所述差分放大器还包括连接到所述第一和第二差分对的输出对的负载电路，用于输出在所述第一和第二差分对的输出对之间的一对连接节点中的至少一个上组合所述第一和第二差分对的输出而获得的信号 第一和第二差分对和负载电路，在第一和第二差分对的输出对和负载电路的连接节点处提供至少一个信号的放大器级，以在输出端输出电压，以及电流 控制电路控制第一和第二电流源，以控制提供给第一和第二差分对的电流比。

公开(公告)号：US20070176675A1

公开(公告)日：2007-08-02

申请号：US11657208

申请日：2007-01-24

申请人： Hiroshi Tsuchi ,  Masao Iriguchi

发明人： Hiroshi Tsuchi ,  Masao Iriguchi

IPC分类号： H03F1/02

CPC分类号： H03F3/45183 ,  H03F1/26 ,  H03F2200/372 ,  H03F2203/45548 ,  H03F2203/45616 ,  H03M1/765

摘要： A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal. First and second switches (SW1 and SW2) are provided between the input pair of the first differential pair and the first and second input terminals (1 and 2), and first and second capacitors (C1 and C2) connected between each connection point of the input pair of the first differential pair and the first and second switches (SW1 and SW2) and a reference voltage terminal are provided. The first, second and third input terminals (1, 2, and 3) may be combined into one terminal to which voltages are serially supplied. It avoids the influence of power supply/signal noise and switch noise, and provides operational output from a plurality of input reference voltages.

摘要翻译： 差分放大器包括由相应的电流源驱动的第一，第二和第三输入端子（1,2和3），输出端子（4），第一和第二差分对（531和532）（533和534） 通常连接到负载电路（537和538）的输出对以及具有连接到负载电路的公共连接点和第一和第二差分对的输出对中的至少一个的输入端的放大器级（539）和输出端 连接到输出端子。 第二差分对的输入对接收来自第三输入端的信号和来自输出端的反馈信号。 第一和第二开关（SW 1和SW 2）设置在第一差分对的输入对与第一和第二输入端（1和2）之间，第一和第二电容器（C 1和C 2） 提供第一差分对和第一和第二开关（SW 1和SW 2）的输入对和参考电压端子的连接点。 第一，第二和第三输入端子（1,2和3）可以组合成串联供应电压的一个端子。 它避免了电源/信号噪声和开关噪声的影响，并提供了多个输入参考电压的工作输出。

公开(公告)号：US20070159250A1

公开(公告)日：2007-07-12

申请号：US11648530

申请日：2007-01-03

申请人： Hiroshi Tsuchi ,  Junichiro Ishii ,  Kouichi Nishimura

发明人： Hiroshi Tsuchi ,  Junichiro Ishii ,  Kouichi Nishimura

IPC分类号： H03F3/45

CPC分类号： H03F3/45233 ,  H03F2203/45726

摘要： A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

摘要翻译： 一种差分放大电路，其包括形成该差分对的负载电路的差分对和共源共栅电流镜电路。 共源共栅电流镜电路包括控制端耦合的第一晶体管对以及在耦合的控制端分别接收第一和第二偏置信号的第二和第三晶体管对。 第二晶体管对直接连接在第一晶体管对与共源共栅电流镜电路的输入端和输出端之间，第三晶体管对交叉连接在第一晶体管对与输入端之间，输出端 的共源共栅电流镜电路。 通过改变第一和第二偏置信号的电压值来控制第二和第三晶体管对，以便各自通过改变第一和第二偏置信号的电压值而被置于有功和无效状态，其中控制是以这样的方式进行的：当这些晶体管对中的一个处于 活动状态，另一个处于非活动状态。

公开(公告)号：US20070085608A1

公开(公告)日：2007-04-19

申请号：US11526636

申请日：2006-09-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  G09G3/3688 ,  G09G2310/027 ,  H03F2203/45616 ,  H03F2203/45631 ,  H03F2203/45656 ,  H03F2203/45682 ,  H03F2203/45728 ,  H03M1/765

摘要： Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input terminal, a fourth switch connected between a gate of the third transistor and a second input terminal, and a fifth switch connected between the gate of the third transistor and the output terminal. Switching control between a first state where the first, second and fourth switches are turned on and the third and fifth switches are turned off and a second state where the first and second fourth switches are turned off and the third and fifth switches are turned on is performed.

摘要翻译： 公开了一种多电平输出型的差分放大器，包括负载电路，负载电路包括二极管连接的第一晶体管，其源极连接到电源，第二晶体管的源极连接到电源并连接到栅极 第一晶体管通过电容器，差分对包括第三晶体管和第四晶体管，其源极分别连接到第一和第二晶体管的漏极，电流源分别连接到第一和第二晶体管的漏极，电流源用于向差分 连接在第二晶体管的栅极和第四晶体管的漏极之间的第一开关，放大器，其输入连接到第二晶体管的漏极，其输出连接到输出端子，第二开关连接在 第四晶体管的栅极和第一输入端子，连接在第四晶体管的栅极之间的第三开关 tor和第三输入端，连接在第三晶体管的栅极和第二输入端之间的第四开关，以及连接在第三晶体管的栅极和输出端之间的第五开关。 在第一，第二和第四开关导通的第一状态和第三和第五开关之间的开关控制被关断，而第一和第二第四开关被断开并且第三和第五开关导通的第二状态是 执行。

公开(公告)号：US20060244710A1

公开(公告)日：2006-11-02

申请号：US11411048

申请日：2006-04-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3266 ,  G09G3/3275 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle. The column driver includes D/A converter circuits for converting video data to gray scale signals, a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle, and an output switch circuit including a plurality of switches connected to output terminals of the buffer amplifiers and the data lines, respectively. The delay control circuit controls the scan driver so that the preset scan cycle is delayed from the preset output cycle just by a preset delay time. The output switch control circuit controls the output switch circuit to be kept off during the preset delay time. The display controller controls the video data, scan driver, column driver, delay control circuit, and output switch control circuit, respectively.

摘要翻译： 公开了一种显示装置，包括显示单元，列驱动器，延迟控制电路，输出开关控制电路和显示控制器。 显示单元包括布置在矩阵形式的多条数据线和多条扫描线与TFT之间的交叉处的多个像素电极。 每个TFT的漏极和源极之一连接到相应的一个像素电极。 每个TFT的漏极和源极中的另一个连接到对应的一条数据线，并且每个TFT的栅极连接到相应的一条扫描线。 扫描驱动器在预设的扫描周期中向扫描线提供扫描信号。 列驱动器包括用于将视频数据转换为灰度信号的D / A转换器电路，用于在预设输出周期中顺序放大并输出灰度信号的多个缓冲放大器，以及包括多个开关的输出开关电路， 缓冲放大器和数据线的输出端。 延迟控制电路控制扫描驱动器，使得预设的扫描周期从预设的输出周期延迟预设的延迟时间。 输出开关控制电路在预设的延迟时间内控制输出开关电路的关断。 显示控制器分别控制视频数据，扫描驱动器，列驱动器，延迟控制电路和输出开关控制电路。