公开(公告)号：US07623054B2

公开(公告)日：2009-11-24

申请号：US11526636

申请日：2006-09-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： H03F3/45183 ,  G09G3/3688 ,  G09G2310/027 ,  H03F2203/45616 ,  H03F2203/45631 ,  H03F2203/45656 ,  H03F2203/45682 ,  H03F2203/45728 ,  H03M1/765

摘要： Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input terminal, a fourth switch connected between a gate of the third transistor and a second input terminal, and a fifth switch connected between the gate of the third transistor and the output terminal. Switching control between a first state where the first, second and fourth switches are turned on and the third and fifth switches are turned off and a second state where the first and second fourth switches are turned off and the third and fifth switches are turned on is performed.

摘要翻译： 公开了一种多电平输出型的差分放大器，包括负载电路，负载电路包括二极管连接的第一晶体管，其源极连接到电源，第二晶体管的源极连接到电源并连接到栅极 第一晶体管通过电容器，差分对包括第三晶体管和第四晶体管，其源极分别连接到第一和第二晶体管的漏极，电流源分别连接到第一和第二晶体管的漏极，电流源用于向差分 连接在第二晶体管的栅极和第四晶体管的漏极之间的第一开关，放大器，其输入连接到第二晶体管的漏极，其输出连接到输出端子，第二开关连接在 第四晶体管的栅极和第一输入端子，连接在第四晶体管的栅极之间的第三开关 tor和第三输入端，连接在第三晶体管的栅极和第二输入端之间的第四开关，以及连接在第三晶体管的栅极和输出端之间的第五开关。 在第一，第二和第四开关导通的第一状态和第三和第五开关之间的开关控制被关断，而第一和第二第四开关被断开，第三和第五开关导通的第二状态是 执行。

公开(公告)号：US20070176675A1

公开(公告)日：2007-08-02

申请号：US11657208

申请日：2007-01-24

申请人： Hiroshi Tsuchi ,  Masao Iriguchi

发明人： Hiroshi Tsuchi ,  Masao Iriguchi

IPC分类号： H03F1/02

CPC分类号： H03F3/45183 ,  H03F1/26 ,  H03F2200/372 ,  H03F2203/45548 ,  H03F2203/45616 ,  H03M1/765

摘要： A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal. First and second switches (SW1 and SW2) are provided between the input pair of the first differential pair and the first and second input terminals (1 and 2), and first and second capacitors (C1 and C2) connected between each connection point of the input pair of the first differential pair and the first and second switches (SW1 and SW2) and a reference voltage terminal are provided. The first, second and third input terminals (1, 2, and 3) may be combined into one terminal to which voltages are serially supplied. It avoids the influence of power supply/signal noise and switch noise, and provides operational output from a plurality of input reference voltages.

摘要翻译： 差分放大器包括由相应的电流源驱动的第一，第二和第三输入端子（1,2和3），输出端子（4），第一和第二差分对（531和532）（533和534） 通常连接到负载电路（537和538）的输出对以及具有连接到负载电路的公共连接点和第一和第二差分对的输出对中的至少一个的输入端的放大器级（539）和输出端 连接到输出端子。 第二差分对的输入对接收来自第三输入端的信号和来自输出端的反馈信号。 第一和第二开关（SW 1和SW 2）设置在第一差分对的输入对与第一和第二输入端（1和2）之间，第一和第二电容器（C 1和C 2） 提供第一差分对和第一和第二开关（SW 1和SW 2）的输入对和参考电压端子的连接点。 第一，第二和第三输入端子（1,2和3）可以组合成串联供应电压的一个端子。 它避免了电源/信号噪声和开关噪声的影响，并提供了多个输入参考电压的工作输出。

公开(公告)号：US20070085608A1

公开(公告)日：2007-04-19

申请号：US11526636

申请日：2006-09-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  G09G3/3688 ,  G09G2310/027 ,  H03F2203/45616 ,  H03F2203/45631 ,  H03F2203/45656 ,  H03F2203/45682 ,  H03F2203/45728 ,  H03M1/765

摘要： Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input terminal, a fourth switch connected between a gate of the third transistor and a second input terminal, and a fifth switch connected between the gate of the third transistor and the output terminal. Switching control between a first state where the first, second and fourth switches are turned on and the third and fifth switches are turned off and a second state where the first and second fourth switches are turned off and the third and fifth switches are turned on is performed.

摘要翻译： 公开了一种多电平输出型的差分放大器，包括负载电路，负载电路包括二极管连接的第一晶体管，其源极连接到电源，第二晶体管的源极连接到电源并连接到栅极 第一晶体管通过电容器，差分对包括第三晶体管和第四晶体管，其源极分别连接到第一和第二晶体管的漏极，电流源分别连接到第一和第二晶体管的漏极，电流源用于向差分 连接在第二晶体管的栅极和第四晶体管的漏极之间的第一开关，放大器，其输入连接到第二晶体管的漏极，其输出连接到输出端子，第二开关连接在 第四晶体管的栅极和第一输入端子，连接在第四晶体管的栅极之间的第三开关 tor和第三输入端，连接在第三晶体管的栅极和第二输入端之间的第四开关，以及连接在第三晶体管的栅极和输出端之间的第五开关。 在第一，第二和第四开关导通的第一状态和第三和第五开关之间的开关控制被关断，而第一和第二第四开关被断开并且第三和第五开关导通的第二状态是 执行。

公开(公告)号：US20060244710A1

公开(公告)日：2006-11-02

申请号：US11411048

申请日：2006-04-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3266 ,  G09G3/3275 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle. The column driver includes D/A converter circuits for converting video data to gray scale signals, a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle, and an output switch circuit including a plurality of switches connected to output terminals of the buffer amplifiers and the data lines, respectively. The delay control circuit controls the scan driver so that the preset scan cycle is delayed from the preset output cycle just by a preset delay time. The output switch control circuit controls the output switch circuit to be kept off during the preset delay time. The display controller controls the video data, scan driver, column driver, delay control circuit, and output switch control circuit, respectively.

摘要翻译： 公开了一种显示装置，包括显示单元，列驱动器，延迟控制电路，输出开关控制电路和显示控制器。 显示单元包括布置在矩阵形式的多条数据线和多条扫描线与TFT之间的交叉处的多个像素电极。 每个TFT的漏极和源极之一连接到相应的一个像素电极。 每个TFT的漏极和源极中的另一个连接到对应的一条数据线，并且每个TFT的栅极连接到相应的一条扫描线。 扫描驱动器在预设的扫描周期中向扫描线提供扫描信号。 列驱动器包括用于将视频数据转换为灰度信号的D / A转换器电路，用于在预设输出周期中顺序放大并输出灰度信号的多个缓冲放大器，以及包括多个开关的输出开关电路， 缓冲放大器和数据线的输出端。 延迟控制电路控制扫描驱动器，使得预设的扫描周期从预设的输出周期延迟预设的延迟时间。 输出开关控制电路在预设的延迟时间内控制输出开关电路的关断。 显示控制器分别控制视频数据，扫描驱动器，列驱动器，延迟控制电路和输出开关控制电路。

公开(公告)号：US07554389B2

公开(公告)日：2009-06-30

申请号：US11657208

申请日：2007-01-24

申请人： Hiroshi Tsuchi ,  Masao Iriguchi

发明人： Hiroshi Tsuchi ,  Masao Iriguchi

IPC分类号： H03F1/02 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/26 ,  H03F2200/372 ,  H03F2203/45548 ,  H03F2203/45616 ,  H03M1/765

摘要： A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal. First and second switches (SW1 and SW2) are provided between the input pair of the first differential pair and the first and second input terminals (1 and 2), and first and second capacitors (C1 and C2) connected between each connection point of the input pair of the first differential pair and the first and second switches (SW1 and SW2) and a reference voltage terminal are provided. The first, second and third input terminals (1, 2, and 3) may be combined into one terminal to which voltages are serially supplied. It avoids the influence of power supply/signal noise and switch noise, and provides operational output from a plurality of input reference voltages.

摘要翻译： 差分放大器包括由相应的电流源驱动的第一，第二和第三输入端子（1,2和3），输出端子（4），第一和第二差分对（531和532）（533和534） 通常连接到负载电路（537和538）的输出对以及具有连接到负载电路的公共连接点和第一和第二差分对的输出对中的至少一个的输入端的放大器级（539）和输出端 连接到输出端子。 第二差分对的输入对接收来自第三输入端的信号和来自输出端的反馈信号。 第一和第二开关（SW1和SW2）设置在第一差分对的输入对与第一和第二输入端（1和2）之间，第一和第二电容器（C1和C2）连接在第一和第二开关 提供第一差分对和第一和第二开关（SW1和SW2）的输入对和参考电压端子。 第一，第二和第三输入端子（1,2和3）可以组合成串联供应电压的一个端子。 它避免了电源/信号噪声和开关噪声的影响，并提供了多个输入参考电压的工作输出。

公开(公告)号：US07936329B2

公开(公告)日：2011-05-03

申请号：US11411048

申请日：2006-04-26

申请人： Masao Iriguchi ,  Hiroshi Tsuchi

发明人： Masao Iriguchi ,  Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3266 ,  G09G3/3275 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle. The column driver includes D/A converter circuits for converting video data to gray scale signals, a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle, and an output switch circuit including a plurality of switches connected to output terminals of the buffer amplifiers and the data lines, respectively. The delay control circuit controls the scan driver so that the preset scan cycle is delayed from the preset output cycle just by a preset delay time. The output switch control circuit controls the output switch circuit to be kept off during the preset delay time. The display controller controls the video data, scan driver, column driver, delay control circuit, and output switch control circuit, respectively.

摘要翻译： 公开了一种显示装置，其包括显示单元，列驱动器，延迟控制电路，输出开关控制电路和显示控制器。 显示单元包括布置在矩阵形式的多条数据线和多条扫描线与TFT之间的交叉处的多个像素电极。 每个TFT的漏极和源极之一连接到相应的一个像素电极。 每个TFT的漏极和源极中的另一个连接到对应的一条数据线，并且每个TFT的栅极连接到相应的一条扫描线。 扫描驱动器在预设的扫描周期中向扫描线提供扫描信号。 列驱动器包括用于将视频数据转换为灰度信号的D / A转换器电路，用于在预设输出周期中顺序放大并输出灰度信号的多个缓冲放大器，以及包括多个开关的输出开关电路， 缓冲放大器和数据线的输出端。 延迟控制电路控制扫描驱动器，使得预设的扫描周期从预设的输出周期延迟预设的延迟时间。 输出开关控制电路在预设的延迟时间内控制输出开关电路的关断。 显示控制器分别控制视频数据，扫描驱动器，列驱动器，延迟控制电路和输出开关控制电路。

公开(公告)号：US07459967B2

公开(公告)日：2008-12-02

申请号：US11535381

申请日：2006-09-26

申请人： Hiroshi Tsuchi ,  Masao Iriguchi

发明人： Hiroshi Tsuchi ,  Masao Iriguchi

IPC分类号： H03F1/02

CPC分类号： H03F3/45183 ,  G09G3/3685 ,  G09G2310/027 ,  H03F3/505 ,  H03F2203/45616 ,  H03F2203/45674 ,  H03F2203/5021 ,  H03F2203/5039

摘要： Disclosed is a multi-level output differential amplifier which includes a first differential pair; a second differential pair; a load circuit commonly connected to output pairs of the first and second differential pairs; first and second current sources for supplying current to the first and second differential pairs, respectively; an amplifier stage for receiving a common output signal of the first and second differential pairs and driving an output terminal by a charging or discharging operation; and a control circuit for controlling changeover of signal inputs to the first and second differential pairs. The data output period includes first and second time periods. In the first time period, a voltage at the output terminal and a reference voltage are applied to first and second differential inputs of the first differential pair; the output-terminal voltage and the reference voltage are stored in first and second capacitors, respectively, connected to the first and second differential inputs of the first differential pair; and first and second voltages are applied to first and second differential inputs of the second differential pair. In the second time period, the first and second differential inputs of the first differential pair are cut off from supply of the output-terminal voltage and supply of the reference voltage and are supplied with the voltages stored in the first and second capacitors, and the output-terminal voltage and a third voltage are applied to the first and second differential inputs of the second differential pair.

摘要翻译： 公开了一种包括第一差分对的多电平输出差分放大器; 第二差分对; 通常连接到第一和第二差分对的输出对的负载电路; 用于分别向第一和第二差分对提供电流的第一和第二电流源; 放大级，用于接收第一和第二差分对的公共输出信号，并通过充电或放电操作驱动输出端; 以及用于控制对第一和第二差分对的信号输入的切换的控制电路。 数据输出周期包括第一和第二时间段。 在第一时间段中，输出端子处的电压和参考电压被施加到第一差分对的第一和第二差分输入; 输出端电压和参考电压分别存储在连接到第一差分对的第一和第二差分输入的第一和第二电容器中; 并且第一和第二电压被施加到第二差分对的第一和第二差分输入。 在第二时间段中，第一差分对的第一和第二差分输入从输出端电压的供给和参考电压的供给中切断，并且被提供存储在第一和第二电容器中的电压，并且 输出端电压和第三电压施加到第二差分对的第一和第二差分输入。

公开(公告)号：US07535294B2

公开(公告)日：2009-05-19

申请号：US11709409

申请日：2007-02-22

申请人： Masao Iriguchi

发明人： Masao Iriguchi

IPC分类号： H03F1/02

CPC分类号： H03F3/45183 ,  H03F3/45753 ,  H03F3/45762 ,  H03F2200/453 ,  H03F2203/45212 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45652 ,  H03F2203/45681 ,  H03F2203/45726

摘要： An offset cancellation amplifier where during a first period of a data output period, an output voltage and a reference voltage are supplied to the gates of a first differential pair, and the output voltage is accumulated in first and second capacitors while an input voltage is supplied in common to the gates of a second differential pair. During a second period, the output voltage is accumulated in the first capacitor, while the reference voltage is accumulated in the second capacitor. During a third period, the gates of the first differential pair cease to be supplied with the output voltage and with the reference voltage, respectively, and are supplied with the voltages accumulated in the first and second capacitors, respectively. The gates of the second differential pair are supplied with the output voltage and with the input voltage, respectively.

摘要翻译： 一种偏移消除放大器，其中在数据输出周期的第一周期期间，将输出电压和参考电压提供给第一差分对的栅极，并且在提供输入电压的同时，将输出电压累积在第一和第二电容器中 与第二差分对的门共同。 在第二时段期间，在第一电容器中积累输出电压，而在第二电容器中积累基准电压。 在第三时段期间，第一差分对的栅极分别不再提供输出电压和参考电压，并分别提供积累在第一和第二电容器中的电压。 第二差分对的栅极分别被提供有输出电压和输入电压。

公开(公告)号：US20080074167A1

公开(公告)日：2008-03-27

申请号：US11902472

申请日：2007-09-21

申请人： Masao Iriguchi

发明人： Masao Iriguchi

IPC分类号： H03K17/00

CPC分类号： H03K17/005 ,  H03F1/32 ,  H03F1/3211 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03F2203/45171 ,  H03F2203/45226 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45616 ,  H03F2203/45726 ,  H03K17/14 ,  H04J3/047

摘要： A selecting circuit having minimal signal distortion caused by non-linearity of semiconductor switching elements includes a plurality of circuit groups each comprising an input terminal (INa); serially connected resistors (R1a, R2a) having a first end connected to the input terminal; a semiconductor switching element (SW1a) having a first end connected to a node between the resistors; and semiconductor switching elements (SW2a, SW3a) having first ends connected to a second end of the resistors (R1a, R2a). The circuit further includes an operational amplifier (OP) having an inverting input terminal to which second ends of semiconductor switching elements (SW1a, SW1b, . . . , SW1n) in respective ones of the circuit groups are connected in common, and an output terminal to which second ends of semiconductor switching elements (SW2a, Sb 2b, . . . , SW2n) in respective ones of the circuit groups are connected in common; and an output terminal (OUT) to which second ends of semiconductor switching elements (SW3a, SW3b, . . . , SW3n) in respective ones of the circuit groups are connected in common.

摘要翻译： 具有由半导体开关元件的非线性引起的信号失真最小的选择电路包括多个电路组，每个电路组包括输入端（INa）; 串联连接的电阻器（R 1 a，R 2 a），其第一端连接到输入端子; 半导体开关元件（SW1a），其第一端连接到所述电阻器之间的节点; 以及具有连接到电阻器（R 1a，R 2a）的第二端的第一端的半导体开关元件（SW2a，SW3a）。 电路还包括具有反相输入端的运算放大器（OP），各个电路组中的半导体开关元件（SW 1 a，SW 1 b，...，SW 1 n）的第二端连接到该反相输入端 公共端子和各个电路组中的半导体开关元件（SW2a，Sb2b，...，SW2n）的第二端共同连接的输出端子; 以及各个电路组中的半导体开关元件（SW3a，SW3b，...，SW3n）的第二端共同连接的输出端子（OUT）。

公开(公告)号：US20070200620A1

公开(公告)日：2007-08-30

申请号：US11709409

申请日：2007-02-22

申请人： Masao Iriguchi

发明人： Masao Iriguchi

IPC分类号： H03F1/02

CPC分类号： H03F3/45183 ,  H03F3/45753 ,  H03F3/45762 ,  H03F2200/453 ,  H03F2203/45212 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45652 ,  H03F2203/45681 ,  H03F2203/45726

摘要： Disclosed is an offset cancellation amplifier which includes a first differential pair, second differential pair, a common load circuit for the two differential pairs, current sources, an amplifier stage, and first and second capacitors. The first capacitor is connected to the gate of one transistor of the first differential pair. During a first period of a data output period, an output voltage and the reference voltage are supplied to the gates of the first differential pair, the second capacitor is disconnected from the gate of the other transistor of the first differential pair. In this state, the output voltage is accumulated in the first and second capacitors. An input voltage is supplied in common to the gates of the second differential pair During the second period, the second capacitor is disconnected from the first capacitor and connected to the gate of the other transistor of the first differential pair. The output voltage is accumulated in the first capacitor, while the reference voltage is accumulated in the second capacitor. During the third period, the gates of the first differential pair cease to be supplied with the output voltage and with the reference voltage, respectively, and are supplied with the voltages accumulated in the first and second capacitors, respectively. The gates of the second differential pair are supplied with the output voltage and with the input voltage, respectively.

摘要翻译： 公开了一种偏移消除放大器，其包括第一差分对，第二差分对，用于两个差分对的公共负载电路，电流源，放大器级以及第一和第二电容器。 第一电容器连接到第一差分对的一个晶体管的栅极。 在数据输出期间的第一期间，输出电压和参考电压被提供给第一差分对的栅极，第二电容器与第一差分对的另一晶体管的栅极断开。 在这种状态下，输出电压累积在第一和第二电容器中。 输入电压共同提供给第二差分对的栅极在第二周期期间，第二电容器与第一电容器断开并连接到第一差分对的另一个晶体管的栅极。 输出电压累积在第一电容器中，而参考电压累积在第二电容器中。 在第三时段期间，第一差分对的门分别停止提供输出电压和参考电压，分别提供积累在第一和第二电容器中的电压。 第二差分对的栅极分别被提供有输出电压和输入电压。