Method of controlling contact load in electronic component mounting apparatus
    37.
    发明授权
    Method of controlling contact load in electronic component mounting apparatus 有权
    控制电子部件安装装置的接触负荷的方法

    公开(公告)号:US07513036B2

    公开(公告)日:2009-04-07

    申请号:US10596218

    申请日:2005-08-31

    IPC分类号: H05K3/30

    摘要: A method of controlling contact load in an apparatus for mounting electronic components on a substrate, in which a head is lowered at high speed to slow down starting position where there is no risk that the electronic component makes contact with the substrate (S1), and from there the head is lowered at low speed until a predetermined target contact load is detected. The process of lowering the head at low speed includes the steps of moving down the head a predetermined distance (S3), measuring load after the step of moving down the head (S5), and determining whether the measured contact load has reached the target contact load (S9). The steps of moving down the head (S3) and measuring the load (S5) are repeated until the measured load reaches the target contact load. The actual load is precisely controlled to be close to a very small set level of target contact load. Accordingly, electronic components using low dielectric constant material are mounted without the risk of damage.

    摘要翻译: 一种控制用于将电子部件安装在基板上的装置中的接触负载的方法,其中头部以高速降低以减慢起始位置,其中电子部件不接触基板的风险(S1);以及 从那里头部以低速降低,直到检测到预定的目标接触负载。 低速降低头部的处理包括以下步骤:使头部向下移动预定距离(S3),测量头部向下移动步骤后的负载(S5),以及确定所测量的接触负载是否已达到目标接触 负载(S9)。 重复下降头部(S3)和测量负载(S5)的步骤,直到测量的负载达到目标接触负载。 实际负载被精确地控制为接近非常小的目标接触负载的设定水平。 因此,使用低介电常数材料的电子部件安装而不会有损坏的危险。

    Logic-circuit layout pattern inspection method and logical simulation
    39.
    发明授权
    Logic-circuit layout pattern inspection method and logical simulation 失效
    逻辑电路布局模式检查方法和逻辑仿真

    公开(公告)号:US5381345A

    公开(公告)日:1995-01-10

    申请号:US935994

    申请日:1992-08-27

    CPC分类号: G06F17/5022 G06F17/5081

    摘要: A circuit layout pattern inspection method and a logical simulator for implementing the same. Wiring is substituted by a .pi. or T equivalent circuit and is described by a nodal equation, and a gate is described by a simplified model, that is, a current source calculation formula. By the nodal equation and the current source calculation formula, a simulation is performed to obtain a delay time for every node. The obtained delay time is stored to make the inspection easy.

    摘要翻译: 电路布局图案检查方法及其实现方法。 接线由pi或T等效电路代替,并由节点方程描述,并且门由简化模型描述,即电流源计算公式。 通过节点方程和电流源计算公式,进行模拟以获得每个节点的延迟时间。 存储所获得的延迟时间以使检查变得容易。