公开(公告)号：US20150136381A1

公开(公告)日：2015-05-21

申请号：US14395974

申请日：2012-04-23

申请人： Takashi Hotta ,  Kenichi Yamada ,  Takayuki Iwakawa

发明人： Takashi Hotta ,  Kenichi Yamada ,  Takayuki Iwakawa

IPC分类号： F28F27/02

CPC分类号： F28F27/02 ,  F01K13/02 ,  F01K23/065 ,  F02G5/02 ,  Y02T10/166

摘要： A heat transport device (1A) is provided with: a circulation path unit (10) in which a heat recovery unit (11) that vaporizing a heat transport medium and a condensation unit (12) that condenses the heat transport medium vaporized in the heat recovery unit (11) are incorporated, and which has a vacuum state; a branch path unit (20) which branches from the circulation path unit (10), and in which a valve (22) capable of controlling flow is incorporated; and an ECU (40A) which implements a first control unit and is configured to, when it is recognized that there is an increase in the pressure within the circulation path unit (10) under the same operating condition, open and close the valve (22) in the state in which the pressure within the circulation path unit (10) is higher than a predetermined pressure (α).

摘要翻译： 热传输装置（1A）具有：循环路径单元（10），其中使热交换介质蒸发的热回收单元（11）和冷凝在热量中蒸发的传热介质的冷凝单元（12） 回收单元（11），其具有真空状态; 分支路径单元（20），其从循环路径单元（10）分支，并且其中结合有能够控制流量的阀（22）; 以及ECU（40A），其实现第一控制单元，并且被构造成当在相同的操作条件下认识到循环路径单元（10）内的压力增加时，打开和关闭阀（22） ）处于循环路径单元（10）内的压力高于预定压力（α）的状态。

公开(公告)号：US07882929B2

公开(公告)日：2011-02-08

申请号：US10594563

申请日：2005-03-15

申请人： Takashi Hotta ,  Tamiyuki Nakane ,  Katsutoshi Kato

发明人： Takashi Hotta ,  Tamiyuki Nakane ,  Katsutoshi Kato

IPC分类号： F02M69/46

CPC分类号： F02M69/465 ,  F02M51/005 ,  F02M55/04 ,  F02M2200/315

摘要： A delivery pipe includes an outer pipe, an inner pipe, and a noise emission decreasing device. The outer pipe is connected to a plurality of fuel injectors. The inner pipe is disposed in the outer pipe and has an open end through which an interior of the inner pipe communicates with atmosphere. The noise emission decreasing device acts so as to decrease a noise emitted from the inner pipe. The noise emission decreasing device includes a mesh, a porous member, a vibration suppressing member provided to the inner pipe, an elastic tube fitted into the inner pipe, or a wire harness inserted into the inner pipe.

摘要翻译： 输送管包括外管，内管和噪声排放减少装置。 外管连接到多个燃料喷射器。 内管设置在外管中，并且具有开口端，内管的内部通过该开口端与大气连通。 噪声发射减少装置用于降低从内管发出的噪声。 噪声减少装置包括网，多孔构件，设置在内管上的振动抑制构件，装配到内管中的弹性管或插入内管中的线束。

公开(公告)号：US06848027B2

公开(公告)日：2005-01-25

申请号：US10426828

申请日：2003-05-01

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US06792583B1

公开(公告)日：2004-09-14

申请号：US09501977

申请日：2000-02-11

申请人： Yoshitaka Takahashi ,  Kotaro Shimamura ,  Takashi Hotta ,  Teppei Hirotsu ,  Katsuichi Tomobe

发明人： Yoshitaka Takahashi ,  Kotaro Shimamura ,  Takashi Hotta ,  Teppei Hirotsu ,  Katsuichi Tomobe

IPC分类号： G06F945

CPC分类号： G06F17/5072

摘要： In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.

摘要翻译： 在信息处理装置中，不知道LSI的设计者的用户在不降低LSI的性能的情况下修改LSI的布局图。 设计LSI的设计者使用电路设计装置来存储包括构成LSI的每个块的功能的电路信息，关于块的分配的平面布置图以及作为设计者的专有技术的评估指标， 与彼此。 用户使用平面图修改装置来修改平面布置图并根据评价指标来评估修改的平面图。

公开(公告)号：US06587927B2

公开(公告)日：2003-07-01

申请号：US09864287

申请日：2001-05-25

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US06484294B1

公开(公告)日：2002-11-19

申请号：US09462913

申请日：2000-01-18

申请人： Yoshikazu Kiyoshige ,  Michinobu Nakao ,  Kazumi Hatayama ,  Takashi Hotta

发明人： Yoshikazu Kiyoshige ,  Michinobu Nakao ,  Kazumi Hatayama ,  Takashi Hotta

IPC分类号： G06F1750

CPC分类号： G01R31/318583 ,  G01R31/3016

摘要： A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

摘要翻译： 一种用于设计半导体集成电路同时最小化其被测逻辑电路的面积的任何增加的方法。 接收关于半导体集成电路的电路数据，并且通过使用电路数据来计算所涉及的所有配备有扫描功能的存储元件的转换信号发生概率。 为了与由此计算出的过渡信号发生概率和基于预定参数保持一致，该方法允许选择可由具有延迟测试就绪扫描功能的存储元件代替的具有扫描功能的存储元件。

公开(公告)号：US06389041B1

公开(公告)日：2002-05-14

申请号：US09205343

申请日：1998-12-04

申请人： Yuichiro Morita ,  Kotaro Shimamura ,  Yoshitaka Takahashi ,  Takashi Hotta ,  Kazuhiro Imaie ,  Shigeta Ueda ,  Akira Bando ,  Mitsuyasu Kido ,  Takeshi Takehara

发明人： Yuichiro Morita ,  Kotaro Shimamura ,  Yoshitaka Takahashi ,  Takashi Hotta ,  Kazuhiro Imaie ,  Shigeta Ueda ,  Akira Bando ,  Mitsuyasu Kido ,  Takeshi Takehara

IPC分类号： G06F1516

CPC分类号： G06F11/184 ,  G06F1/12 ,  G06F11/0736 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/165 ,  G06F11/1675

摘要： In a synchronization system adopted in a synchronous-multisystem control apparatus including a plurality of systems operating synchronously with each other at a fixed control period, the synchronous-multisystem control apparatus can be operated in a single-system mode in the event of failures occurring simultaneously in some of the systems. The synchronous-multisystem control apparatus employs a plurality of control circuits each provided for one of the systems. Any particular one of the control circuits includes: a period-signal generating circuit for generating a period signal indicating a start point of a control period; a synchronization-reference selecting circuit for outputting a synchronization-reference signal by referring to period signals generated by the systems; and a control-period correcting circuit for correcting a control period of the particular system by forming a judgment on a synchronization shift of the period signal generated by the particular system from the synchronization-reference signal and keeping the control period as it is in case the synchronization-reference signal is not generated.

摘要翻译： 在同步多系统控制装置中采用的同步系统控制装置中，包括在固定的控制周期中彼此​​同步操作的多个系统，同步多系统控制装置可以在同时发生故障的情况下以单一系统模式操作 在一些系统中。 同步多系统控制装置采用多个控制电路，每个控制电路为系统之一提供。 任何一个控制电路包括：周期信号发生电路，用于产生指示控制周期的起始点的周期信号; 同步参考选择电路，用于通过参考系统产生的周期信号来输出同步参考信号; 以及控制周期校正电路，用于通过根据同步参考信号形成对由特定系统产生的周期信号的同步偏移的判断来校正特定系统的控制周期，并且保持控制周期为原样， 不产生同步参考信号。

公开(公告)号：US5848432A

公开(公告)日：1998-12-08

申请号：US281002

申请日：1994-07-27

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US5784630A

公开(公告)日：1998-07-21

申请号：US367928

申请日：1995-01-03

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

公开(公告)号：US5643126A

公开(公告)日：1997-07-01

申请号：US627673

申请日：1996-04-01

申请人： Takashi Hotta ,  Kinji Marumo ,  Michio Kojima

发明人： Takashi Hotta ,  Kinji Marumo ,  Michio Kojima

IPC分类号： F16H3/44 ,  F16H57/04 ,  F16H57/08

CPC分类号： F16H57/0482 ,  F16H57/0479 ,  F16H57/082

摘要： A planetary gear mechanism includes a planetary carrier and pinions rotatably carried on the planetary carrier through pinion shafts. An annular lubricating oil supply member is mounted on a ring gear supporting member which supports a ring gear on its outer periphery and which is rotatable. The lubricating oil supply member has a plurality of fins formed radially thereon. The lubricating oil received within the lubricating oil supply member while submerged in the lubricating oil is scattered by a centrifugal force and supplied to oil reservoirs defined in the adjacent side of the planetary carrier and then from the oil reservoirs via oil passages in the pinion shafts to the needle bearing which supports the pinions. With the above construction, it is possible to effectively supply the lubricating oil to the pinion shafts of the planetary gear mechanism when the planetary is in a fixed position.

摘要翻译： 行星齿轮机构包括行星架和通过小齿轮轴可旋转地承载在行星架上的小齿轮。 环形润滑油供给部件安装在环形齿轮支撑部件上，该齿圈支撑部件在其外周上支撑环形齿轮并且可旋转。 润滑油供给部件具有径向地形成的多个翅片。 润滑油供给部件内的润滑油在浸没在润滑油中时被离心力散射，供给到在行星齿轮架的相邻侧限定的油箱，然后通过小齿轮轴上的油路从储油器传递到 支撑小齿轮的滚针轴承。 通过上述结构，当行星齿轮处于固定位置时，能够有效地将润滑油供给行星齿轮机构的小齿轮轴。