公开(公告)号：US08471973B2

公开(公告)日：2013-06-25

申请号：US12788876

申请日：2010-05-27

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC: G02F1/36

CPC classification number: G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract translation: 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20130126871A1

公开(公告)日：2013-05-23

申请号：US13402883

申请日：2012-02-23

Applicant: Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

Inventor： Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

IPC: H01L33/58

CPC classification number: H01L33/58 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255

Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract translation: 像素结构包括在基板上的第一电极，覆盖第一电极的第一绝缘层，位于第一绝缘层上的栅极，位于第一电极上方的第一绝缘层上的第二电极，覆盖栅极的第二绝缘层 并且第二电极，位于栅极上方的第二绝缘层上的半导体层，位于半导体层上的源极和漏极，第三电极，第三绝缘层和像素电极。 第三电极位于第二电极上方的第二绝缘层上并与第一电极电连接。 第三绝缘层覆盖源极，漏极和第三电极。 像素电极位于第三绝缘层上并与漏极电连接。

公开(公告)号：US20120293953A1

公开(公告)日：2012-11-22

申请号：US13193117

申请日：2011-07-28

Applicant: Chun-Che Wu ,  Chun-Nan Su ,  Chih-Hung Lin ,  Chung-Chun Wu

Inventor： Chun-Che Wu ,  Chun-Nan Su ,  Chih-Hung Lin ,  Chung-Chun Wu

IPC: H05K5/02

CPC classification number: F16M11/10 ,  A45C11/00 ,  A45C2011/003 ,  F16M13/00 ,  G06F1/1632 ,  G06F2200/1633

Abstract: A storage device for a tablet personal computer is provided. The storage device includes a base and an upper cover for fixing the tablet personal computer. The base includes a foldable structure. When the foldable structure is folded and stacked on a side of the base, a receiving space for fixing a keyboard device is defined by the base and the foldable structure. In such way, the tablet personal computer and the keyboard device can be simultaneously stored within the storage device.

Abstract translation: 提供了一种用于平板电脑的存储设备。 存储装置包括用于固定平板电脑的基座和上盖。 底座包括可折叠结构。 当可折叠结构被折叠并堆叠在基座的一侧时，用于固定键盘装置的接收空间由基座和可折叠结构限定。 以这种方式，平板电脑和键盘装置可以同时存储在存储装置内。

公开(公告)号：US20120092240A1

公开(公告)日：2012-04-19

申请号：US13330627

申请日：2011-12-19

Applicant: Chih-Hung Lin ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Che-Chia Chang ,  Sheng-Chao Liu ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Maw-Song Chen

Inventor： Chih-Hung Lin ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Che-Chia Chang ,  Sheng-Chao Liu ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Maw-Song Chen

IPC: G09G3/36 ,  H03B1/00

CPC classification number: G02F1/133707 ,  G02F1/136213 ,  G02F2201/40

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a first insulating layer, a pixel electrode, a capacitor electrode, and a second insulating layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the first insulating layer. The second insulating layer is located between the capacitor electrode and the drain.

Abstract translation: 提供有源器件，像素结构和显示面板。 像素结构包括扫描线，数据线，有源器件，第一绝缘层，像素电极，电容器电极和第二绝缘层。 有源器件包括栅极，沟道，源极和漏极。 栅极电连接到扫描线。 源电连接到数据线。 第一绝缘层设置在栅极和沟道之间。 像素电极电连接到漏极。 电容电极位于第一绝缘层上。 第二绝缘层位于电容器电极和漏极之间。

公开(公告)号：US20120002138A1

公开(公告)日：2012-01-05

申请号：US13067763

申请日：2011-06-24

Applicant: Chih-Hung Lin ,  Chia Hui Yu

Inventor： Chih-Hung Lin ,  Chia Hui Yu

IPC: G02F1/13357 ,  F21V7/22 ,  G02B6/26 ,  C09D11/10

CPC classification number: C09D11/106 ,  C09D11/101 ,  G02B6/0043 ,  G02B6/0065

Abstract: The present invention relates to a pattern forming ink composition, and more particularly, to a pattern forming ink composition having high yellowing resistance, wherein the pattern forming ink composition including an acrylate-based resin having a ring structure (A), a compound having at least one ethylenically unsaturated double bond (B) and a photoinitiator (C). The pattern forming ink is printed as a reflection pattern on a light guide plate to scatter and reflect the light incident to the reflection pattern towards a light emitting surface of the light guide plate.

Abstract translation: 本发明涉及图案形成油墨组合物，更具体地说，涉及具有高耐黄变性的图案形成油墨组合物，其中，图案形成油墨组合物包括具有环结构（A）的丙烯酸酯类树脂，具有 至少一个烯属不饱和双键（B）和光引发剂（C）。 图案形成油墨作为反射图案印刷在导光板上，以将入射到反射图案的光朝向导光板的发光表面散射并反射。

公开(公告)号：US07986931B2

公开(公告)日：2011-07-26

申请号：US11736008

申请日：2007-04-17

Applicant: Chih-Hung Lin ,  Chin-Fu Li ,  Chia-Jen Yu ,  Jiunn-Tsair Chen

Inventor： Chih-Hung Lin ,  Chin-Fu Li ,  Chia-Jen Yu ,  Jiunn-Tsair Chen

IPC: H04B7/00

CPC classification number: G06K7/0008 ,  G06K7/10346

Abstract: An echo cancellation circuit for an RFID reader and the method thereof are provided. The echo cancellation circuit includes a gain calculator, a gain adjustment circuit, and a subtraction circuit. The gain calculator provides a complex gain value according to a carrier signal and a received signal through an adaptive algorithm. The gain adjustment circuit is coupled to the gain calculator. The gain adjustment circuit multiplies the carrier signal by the complex gain value, and outputs the result of the multiplication. The subtraction circuit is coupled to the gain adjustment circuit. The subtraction circuit subtracts the output of the gain adjustment circuit from the received signal, and then provides the result of the subtraction as the output signal of the echo cancellation circuit.

Abstract translation: 提供了一种用于RFID读取器的回波消除电路及其方法。 回波消除电路包括增益计算器，增益调整电路和减法电路。 增益计算器通过自适应算法根据载波信号和接收信号提供复数增益值。 增益调整电路耦合到增益计算器。 增益调整电路将载波信号乘以复数增益值，并输出乘法结果。 减法电路耦合到增益调整电路。 减法电路从接收信号中减去增益调整电路的输出，然后将减法结果作为回波消除电路的输出信号。

公开(公告)号：US20110023120A1

公开(公告)日：2011-01-27

申请号：US12571447

申请日：2009-10-01

Applicant: Shih-Yao Dai ,  Yu-Chen Chang ,  Jain-Shing Wu ,  Chih-Hung Lin ,  Yen-Nun Huang ,  Sy-Yen Kuo

Inventor： Shih-Yao Dai ,  Yu-Chen Chang ,  Jain-Shing Wu ,  Chih-Hung Lin ,  Yen-Nun Huang ,  Sy-Yen Kuo

IPC: G06F12/14

CPC classification number: G06F21/56 ,  G06F21/568

Abstract: A method and a system for cleaning malicious software (malware), a computer program product, and a storage medium are provided. A relation graph is established to associate processes in an operating system and related elements. A node marking action is performed on the relation graph when a predetermined condition is satisfied. The node corresponding to a malicious process and its related nodes are marked with a first label. The nodes of other normal processes and their related nodes are marked with a second label. Then, those nodes marked with both the first label and the second label are screened, so that each of the nodes is marked with only the first label or the second label. Finally, the processes and elements corresponding to the nodes marked with the first label are removed.

Abstract translation: 提供了一种用于清洁恶意软件（恶意软件），计算机程序产品和存储介质的方法和系统。 建立关系图以将操作系统中的过程和相关元素相关联。 当满足预定条件时，在关系图上执行节点标记动作。 对应于恶意进程的节点及其相关节点标有第一个标签。 其他正常进程的节点及其相关节点标有第二个标签。 然后，屏蔽标记有第一标签和第二标签的节点，使得每个节点仅标记第一标签或第二标签。 最后，删除与标记有第一个标签的节点对应的进程和元素。

公开(公告)号：US07733978B2

公开(公告)日：2010-06-08

申请号：US11420482

申请日：2006-05-26

Applicant: Chih-Hung Lin ,  Jiunn-Tsair Chen

Inventor： Chih-Hung Lin ,  Jiunn-Tsair Chen

IPC: H04K1/02

CPC classification number: H03F1/3247 ,  H03F2201/3233

Abstract: A digital adaptive predistorter look up table (DAPD-LUT) technique dynamically adapts a look up table (LUT) an LUT spacing for linearizing a power amplifier (PA). It optimizes the LUT spacing for the PA without prior knowledge of system state information. A size-N LUT divides a whole unsaturated PA input amplitude range into N bins, each predistorted by an entry of the LUT. The LUT is indexed by an input amplitude of a modulated signal via an index mapper to implement an unconditionally non-uniform LUT spacing. A spacing adaptor online interactively adapts the LUT spacing. The adapted LUT spacing balances the inter-modulation distortion (IMD) power at the PA output corresponding to each bin, so that the total IMD power at the PA output is minimized. This dynamically-optimum technique is practical, robust, and with low complexity.

Abstract translation: 数字自适应预失真器查找表（DAPD-LUT）技术动态地将查找表（LUT）用于线性化功率放大器（PA）的LUT间隔。 它优化了PA的LUT间距，而无需系统状态信息的知识。 尺寸N LUT将整个不饱和PA输入幅度范围划分为N个存储区，每个存储块由LUT的条目预失真。 LUT通过索引映射器的调制信号的输入幅度进行索引，以实现无条件不均匀的LUT间隔。 在线间距适配器交互式地适应LUT间隔。 适配的LUT间隔平衡对应于每个仓的PA输出端的互调失真（IMD）功率，使得PA输出端的总IMD功率最小化。 这种动态优化的技术是实用的，稳健的，复杂度低的。

公开(公告)号：US07610535B2

公开(公告)日：2009-10-27

申请号：US11747922

申请日：2007-05-14

Applicant: Yu-Jen Huang ,  Chih-Hung Lin

Inventor： Yu-Jen Huang ,  Chih-Hung Lin

IPC: G01R31/309 ,  G01R31/40

CPC classification number: G06F17/5077 ,  G01R31/2815 ,  G01R31/318591 ,  G06F17/5081 ,  G06F2217/40

Abstract: Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA.

Abstract translation: 阅读PCBA的描述文件，而无需确定和选择可能与边界扫描相关的连接器。 PCBA的描述文件确定PCBA上的连接器的哪些引脚应对应于测试I / O模块的引脚。 并使用自动测试程序生成器生成的接线报告将测试I / O模块的引脚对应到通过边界扫描访问的连接器的引脚。 因此，测试I / O模块的IC在连接到PCBA的连接器的任何两个连续引脚之间不会有任何未使用的引脚。

公开(公告)号：US20080136645A1

公开(公告)日：2008-06-12

申请号：US11736008

申请日：2007-04-17

Applicant: Chih-Hung Lin ,  Chin-Fu Li ,  Chia-Jen Yu ,  Jiunn-Tsair Chen

Inventor： Chih-Hung Lin ,  Chin-Fu Li ,  Chia-Jen Yu ,  Jiunn-Tsair Chen

IPC: G08B1/08

CPC classification number: G06K7/0008 ,  G06K7/10346

Abstract: An echo cancellation circuit for an RFID reader and the method thereof are provided. The echo cancellation circuit includes a gain calculator, a gain adjustment circuit, and a subtraction circuit. The gain calculator provides a complex gain value according to a carrier signal and a received signal through an adaptive algorithm. The gain adjustment circuit is coupled to the gain calculator. The gain adjustment circuit multiplies the carrier signal by the complex gain value, and outputs the result of the multiplication. The subtraction circuit is coupled to the gain adjustment circuit. The subtraction circuit subtracts the output of the gain adjustment circuit from the received signal, and then provides the result of the subtraction as the output signal of the echo cancellation circuit.

Abstract translation: 提供了一种用于RFID读取器的回波消除电路及其方法。 回波消除电路包括增益计算器，增益调整电路和减法电路。 增益计算器通过自适应算法根据载波信号和接收信号提供复数增益值。 增益调整电路耦合到增益计算器。 增益调整电路将载波信号乘以复数增益值，并输出乘法结果。 减法电路耦合到增益调整电路。 减法电路从接收信号中减去增益调整电路的输出，然后将减法结果作为回波消除电路的输出信号。